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| an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 tps6130xx 1.5-a and 4.1-a multiple led camera flash driver with i 2 c compatible interface 1 1 features 1 ? four operational modes ? dc light and flashlight ? voltage regulated converter: 3.8 v to 5.7 v ? standby: 2 a (typical) ? storage capacitor friendly solution ? automatic v f and esr calibration ? power-save mode for improved efficiency at low output power, up to 95% efficiency ? output voltage remains regulated when input voltage exceeds nominal output voltage ? i 2 c compatible interface up to 3.4 mbits/s ? zero latency tx-masking input ? hardware voltage mode selection input (tps61300, tps61301) ? dc light mode selection input (tps61300, tps61306) ? hardware reset input (tps61301, tps61305) ? led temperature monitoring (tps61305) ? privacy indicator led output ? integrated led safety timer ? total solution size of less than 25 mm 2 ( < 1 mm height) ? available in a 20-pin nanofree ? (dsbga) 2 applications ? single, dual, or triple white led flashlight supply for cell phones and smart-phones ? led based xenon killer flashlight ? audio amplifier power supply 3 description the tps6130xx device is based on a high-frequency synchronous boost topology with constant current sinks to drive up to three white leds in parallel (400 ? ma, 800-ma, and 400-ma maximum flash current). the extended high-current mode (hc_sel) allows up to 1025-ma, 2050-ma, and 1025-ma flash current out of the storage capacitor. the high-capacity storage capacitor on the output of the boost regulator provides the high-peak flash led current, thereby reducing the peak current demand from the battery to a minimum. the 2-mhz switching frequency allows the use of small and low profile 2.2- h inductors. to optimize overall efficiency, the device operates with a 400-mv led feedback voltage. the tps6130xx device not only operates as a regulated current source, but also as a standard voltage boost regulator. the device keeps the output voltage regulated even when the input voltage exceeds the nominal output voltage. the device enters power-save mode operation at light load currents to maintain high efficiency over the entire load current range. to simplify flashlight synchronization with the camera module, the device offers a trigger pin (flash_sync) for zero latency led turnon time. table 1. device information (1) part number package body size (nom) tps6130xx dsbga (20) 1.90 mm 2.20 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. figure 1. simplified schematic vout avin sw c i sw led1 c o 10 m f pgnd pgnd agnd l 2.2 h m sda scl tps61300 led2 led3 d2 2. 5 v.. 5 . 5 v endcl flash_sync tx- mask gpio/pg envm indled privacy indicator camera engine i 2 c i/f hc_sel bal flash ready phone power on 1.8 v super-cap d1 copyright ? 2016, texas instruments incorporated productfolder sample &buy technical documents tools & software support &community
2 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 device comparison table ..................................... 3 6 pin configuration and functions ......................... 3 7 specifications ......................................................... 5 7.1 absolute maximum ratings ...................................... 5 7.2 esd ratings .............................................................. 5 7.3 recommended operating conditions ....................... 5 7.4 thermal information .................................................. 5 7.5 electrical characteristics ........................................... 6 7.6 timing requirements ................................................ 8 7.7 typical characteristics ............................................ 11 8 detailed description ............................................ 16 8.1 overview ................................................................. 16 8.2 functional block diagrams ..................................... 17 8.3 feature description ................................................. 22 8.4 device functional modes ........................................ 30 8.5 register maps ......................................................... 39 9 application and implementation ........................ 50 9.1 application information ............................................ 50 9.2 typical applications ................................................ 50 9.3 system examples ................................................... 58 10 power supply recommendations ..................... 62 11 layout ................................................................... 62 11.1 layout guidelines ................................................. 62 11.2 layout example .................................................... 63 11.3 thermal considerations ........................................ 63 12 device and documentation support ................. 64 12.1 related links ........................................................ 64 12.2 community resources .......................................... 64 12.3 trademarks ........................................................... 64 12.4 electrostatic discharge caution ............................ 64 12.5 glossary ................................................................ 64 13 mechanical, packaging, and orderable information ........................................................... 64 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision d (october 2012) to revision e page ? added esd ratings table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section .................................................................................................. 1 changes from revision c (august 2012) to revision d page ? added note specifying silicon revision id bits can differ depending on the product die revision number. ........................... 49 changes from revision b (september 2011) to revision c page ? changed active cell balancing circuitry maximum quiescent current into vout from 3.0 to 6.0 a ..................................... 7 ? added additional information related to the dc-dc input current limiting scheme. ............................................................. 36 ? added additional information related to the dc-dc input current limiting scheme. ............................................................. 36 ? added note 2 to register1 description (tps61300, tps61301) table ..................................................................... 40 ? added note 2 to register1 description (tps61305, tps61306) table ..................................................................... 41 changes from revision a (september 2010) to revision b page ? changed i stby max current from 5 a to 12 a .................................................................................................................... 6 changes from original (june 2009) to revision a page ? deleted product preview device number tps61306 from data sheet header. ....................................................................... 1 3 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 5 device comparison table (1) for more details, see feature description . (2) device status is product preview. contact ti for more details. package marking device specific features (1) tps61300 hardware enable dc light input (endcl) tps61301 hardware enable / disable input (nreset) tps61305 hardware enable / disable input (nreset) led temperature monitoring input (ts) tps61305a hardware enable / disable input (nreset) led temperature monitoring input (ts) tps61306 (2) hardware enable dc light input (endcl) led temperature monitoring input (ts) 6 pin configuration and functions tps61300 yff package 20-pin dsbga top view tps61305 and tps61305a yff package 20-pin dsbga top view tps61301 yff package 20-pin dsbga top view tps61306 yff package 20-pin dsbga top view a b c d e 4 3 2 1 agnd flash_sync ts gpio/pg avin bal hc_sel tx-mask endcl led3 vout scl sw pgnd led1 indled sda sw pgnd led2 a b c d e 4 3 2 1 agnd flash_sync ts gpio/pg avin bal hc_sel tx-mask nreset led3 vout scl sw pgnd led1 indled sda sw pgnd led2 a b c d e 4 3 2 1 agnd flash_sync envm gpio/pg avin bal hc_sel tx-mask nreset led3 vout scl sw pgnd led1 indled sda sw pgnd led2 a b c d e 4 3 2 1 agnd flash_sync envm gpio/pg avin bal hc_sel tx-mask endcl led3 vout scl sw pgnd led1 indled sda sw pgnd led2 4 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated (1) applicable to the tps61300 and tps61306 only. (2) applicable to the tps61300 and tps61301 only. (3) applicable to the tps61301 and tps61305a only. (4) applicable to the tps61305a and tps61306 only. table 2. pin functions pin i/o description name no. agnd a4 ? analog ground. avin e4 i this is the input voltage pin of the device. connect directly to the input bypass capacitor. bal a3 o balancing output for dual cells super-capacitor. in steady-state operation, this output compensates for leakage current mismatch between the cells. endcl (1) d3 i hardware control pin for dc light operation. pulling this pin high forces the device into dc light operation. the endcl input is only active when the device is programmed into shutdown or voltage mode regulation. led1 ? 3 inputs are controlled according to enled[3:1] bit settings. envm (2) c4 i enable pin for voltage mode converter. pulling this pin high forces the device into voltage regulation mode (v out is preset to a fixed value, 4.95 v). flash_sync b4 i flashlight strobe pulse synchronization input. flash_sync = low: the device is operating and regulating the led current to the dc light current level (dclc). flash_sync = high: the device is operating and regulating the led current to the flashlight current level (fc). gpio/pg d4 i/o this pin can either be configured as a general purpose input/output pin (gpio) or either as an open- drain or a push-pull output to signal when the converters output voltage is within the regulation limits (pg). per default, the pin is configured as an open-drain power-good output. hc_sel b3 i extended high-current mode selection input. this pin must not be left floating and must be terminated. hc_sel = low: led direct drive mode. the power stage is active and the maximum led currents are defined as 400 ma (iled1), 800 ma (iled2), and 400 ma (iled3). hc_sel = high: energy storage mode. in flash mode, the power stage is either active with reduced current capability or disabled. the maximum led current is defined as 925 ma (iled1), 1850 ma (iled2), and 925 ma (iled3). indled a1 o this pin provides a constant current source to drive low v f leds. connect to led anode. led1 e2 i led return input. this feedback pin regulates the led current through the internal sense resistor by regulating the voltage across it. the regulation operates with typically 400-mv (hc_sel = l) or 400- mv (hc_sel = h) dropout voltage. connect to the cathode of the leds. led2 e1 i led3 e3 i nreset (3) d3 i master hardware reset input. nreset = low: the device is forced in shutdown mode and the i 2 c control i/f is reset. nreset = high: the device is operating normally under the control of the i 2 c interface. pgnd d1, d2 ? power ground. connect to agnd underneath ic. scl b2 i serial interface clock line. this pin must not be left floating and must be terminated. sda b1 i/o serial interface address/data line. this pin must not be left floating and must be terminated. sw c1, c2 i/o inductor connection. drain of the internal power mosfet. connect to the switched side of the inductor. sw is high impedance during shutdown. ts (4) c4 i/o ntc resistor connection. this pin can be used to monitor the led temperature. connect a 220-k ? ntc resistor from the ts input to ground. in case this functionality is not desired, the ts input must be tied to avin or left floating. tx-mask c3 i rf pa synchronization control input. pulling this pin high turns the led from flashlight to dc light operation, thereby reducing almost instantaneously the peak current loading from the battery. vout a2 o this is the output voltage pin of the converter. 5 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. (3) in applications where high power dissipation or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. maximum ambient temperature [t a(max) ] is dependent on the maximum operating junction temperature [t j(max) ], the maximum power dissipation of the device in the application [p d(max) ], and the junction-to-ambient thermal resistance of the part and package in the application ( ja ), as given by the following equation: t a(max) = t j(max) ? ( ja p d(max) ) 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit voltage range (2) avin, vout, sw, led1, led2, led3, scl, sda, flash_sync, endcl, nreset, envm, gpio/pg, hc_sel, tx-mask, ts, bal ? 0.3 7 v current on gpio/pg 25 ma power dissipation internally limited operating ambient temperature (3) , t a ? 40 85 c maxium operating junction temperature, t j(max) 150 c storage temperature, t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 500 7.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min max unit t j operating junction temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 7.4 thermal information thermal metric (1) tps6130xx unit yff (dsbga) 20 pins r ja junction-to-ambient thermal resistance 70.9 c/w r jc(top) junction-to-case (top) thermal resistance 0.4 c/w r jb junction-to-board thermal resistance 11.4 c/w jt junction-to-top characterization parameter 1.9 c/w jb junction-to-board characterization parameter 11.2 c/w 6 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated (1) verified by characterization. not tested in production. 7.5 electrical characteristics unless otherwise noted the specification applies for v in = 3.6 v over an operating junction temperature t j = ? 40 c to 125 c; circuit of (unless otherwise noted). typical values are for t j = 25 c. parameter test conditions min typ max unit supply current v in input voltage range 2.5 5.5 v i q operating quiescent current into avin i out = 0 ma, device not switching ? 40 c t j 85 c 590 700 a i out(dc) = 0 ma, pwm operation v out = 4.95 v, voltage regulation mode 11.3 ma i sd shutdown current hc_sel = 0, ? 40 c t j 85 c 1 5 a i stby standby current hc_sel = 1, storage capacitor balanced ? 40 c t j 85 c 2 12 a precharge current v out = 2.3 v, 2.5 v v in 5.5 v 150 ma precharge hysteresis (referred to v out ) 40 75 mv v uvlo undervoltage lockout threshold (analog circuitry) v in falling 2.3 2.4 v output v out output voltage range current regulation mode vin 5.5 v voltage regulation mode 3.825 5.7 internal feedback voltage accuracy 2.5 v v in 4.8 v, ? 20 c t j 125 c boost mode, pwm voltage regulation ? 2% 2% 0.85 power-save mode ripple voltage i out = 10 ma 0.015 v out v p ? p ovp output overvoltage protection v out rising, 0000 ov[3:0] 0100 4.5 4.65 4.8 v v out rising, 0101 ov[3:0] 1111 5.8 6 6.2 output overvoltage protection hysteresis v out falling, 0101 ov[3:0] 1111 0.15 power switch r ds(on) switch mosfet on-resistance v out = v gs = 3.6 v 90 m ? rectifier mosfet on-resistance v out = v gs = 3.6 v 135 m ? i lkg(sw) leakage into sw v out = 0 v, sw = 3.6 v, ? 40 c t j 85 c 0.3 4 a i lim rectifier valley current limit (open loop) vout = 4.95 v, hc_sel = 0, ? 20 c t j 85 c pwm operation, relative to selected ilim ? 15% 15% oscillator f osc oscillator frequency 1.92 mhz f acc oscillator frequency ? 10% 7% thermal shutdown, hot die detector thermal shutdown (1) 140 160 c thermal shutdown hysteresis (1) 20 c hot die detector accuracy (1) ? 8 8 c 7 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated electrical characteristics (continued) unless otherwise noted the specification applies for v in = 3.6 v over an operating junction temperature t j = ? 40 c to 125 c; circuit of (unless otherwise noted). typical values are for t j = 25 c. parameter test conditions min typ max unit led current regulator led1/3 current accuracy (1) hc_sel = 0 0.4 v v led1/3 2 v 00 dclc13[1:0] 11, t j = 85 c ? 10% 10% 0.4 v v led1/3 2 v 00 fc13[1:0] 11, t j = 85 c ? 7.5% 7.5% led2 current accuracy (1) 0.4 v v led2 2 v 000 dclc2[2:0] 111, t j = 85 c ? 10% 10% 0.4 v v led2 2 v 000 fc2[2:0] 111, t j = 85 c ? 7.5% 7.5% led1/3 current accuracy (1) hc_sel = 1 0.4 v v led1/3 2 v 00 dclc13[1:0] 11, t j = 85 c ? 10% 10% 0.4 v v led1/3 2 v 00 fc13[1:0] 11, t j = 85 c ? 10% 10% led2 current accuracy (1) 0.4 v v led2 2 v 000 dclc2[2:0] 111, t j = 85 c ? 10% 10% 0.4 v v led1/3 2 v 000 fc2[2:0] 111, t j = 85 c ? 10% 10% led1/3 current matching (1) ? 10% 10% led1/2/3 current temperature coefficient 0.05 %/ c indled current accuracy 1.5 v (vin ? vindled) 2.5 v 2.6 ma iindled 7.9 ma, t j = 25 c ? 20% 20% indled current temperature coefficient 0.04 %/ c v do led1/2/3 sense voltage i led1 ? 3 = full-scale current, hc_sel = 0 400 mv led1/2/3 sense voltage i led1 ? 3 = full-scale current, hc_sel = 1 400 450 vout dropout voltage i out = ? 7.5 ma, device not switching 220 led1/2/3 input leakage current v led1/2/3 = v out = 5 v, ? 40 c t j 85 c 0.1 4 a indled input leakage current v indled = 0 v, ? 40 c t j 85 c 0.1 1 a storage capacitor active cell balancing active cell balancing circuitry quiescent current into vout hc_sel = 1, storage capacitor balanced ? 40 c t j 85 c 1.7 6 a active cell balancing accuracy (vout ? bal) vs bal voltage difference storage capacitor balanced hc_sel = 1 v out = 5.7 v ? 100 100 mv bal output drive capability v out = 4.95 v, sink and source current 10 15 ma active discharge resistor hc_sel = 0, device in shutdown mode vout to bal and bal to gnd 0.85 1.5 k ? led temperature monitoring (tps61305, tps61035a) i o(ts) temperature sense current source thermistor bias current 23.8 a ts resistance (warning temperature) ledwarn bit = 1, t j 25 c 39 44.5 50 k ? ts resistance (hot temperature) ledhot bit = 1, t j 25 c 12.5 14.5 16.5 k ? sda, scl, gpio/pg, envm, tx-mask, endcl, nreset, flash_sync, hc_sel v (ih) high-level input voltage 1.2 v v (il) low-level input voltage 0.4 v v (ol) low-level output voltage (sda) i ol = 8 ma 0.3 v low-level output voltage (gpio) dir = 1, i ol = 5 ma 0.3 v (oh) high-level output voltage (gpio) dir = 1, gpiotype = 0, i oh = 8 ma v in ? 0.4 v 8 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated electrical characteristics (continued) unless otherwise noted the specification applies for v in = 3.6 v over an operating junction temperature t j = ? 40 c to 125 c; circuit of (unless otherwise noted). typical values are for t j = 25 c. parameter test conditions min typ max unit (2) settling time to 15% of the target value. i (lkg) logic input leakage current input connected to vin or gnd ? 40 c t j 85 c 0.01 0.1 a r pd envm pull-down resistance envm 0.4 v 350 k ? endcl, nreset pull-down resistance endcl, nreset 0.4 v 350 flash_sync pull-down resistance flash_sync 0.4 v 350 tx-mask pull-down resistance tx-mask 0.4 v 350 hc_sel pull-down resistance hc_sel 0.4 v 350 c (in) sda input capacitance sda = vin or gnd 9 pf scl input capacitance scl = vin or gnd 4 gpio/pg input capacitance dir = 0, gpio/pg = vin or gnd 9 envm input capacitance envm = vin or gnd 4 endcl input capacitance endcl = vin or gnd 3 hc_sel input capacitance hc_sel = vin or gnd 3.5 tx-mask input capacitance tx-mask = vin or gnd 4 flash_sync input capacitance flash_sync = vin or gnd 3 timing t nreset reset pulse width 10 s start-up time from shutdown into dc light mode hc_sel = 0, i led = 100 ma 1.4 ms from shutdown into voltage mode through envm, hc_sel = 0, i out = 0 ma 550 s led current settling time (2) triggered by a rising edge on flash_sync mode_ctrl[1:0] = 10, hc_sel = 0 i led2 = from 0 ma to 800 ma 400 s mode_ctrl[1:0] = 10, hc_sel = 1 i led2 = from 0 ma to 1800 ma 16 led current settling time (2) triggered by tx-mask mode_ctrl[1:0] = 10, hc_sel = 0 i led2 = from 800 ma to 350 ma 15 s 7.6 timing requirements parameter test conditions min max unit f (scl) scl clock frequency standard mode 100 khz fast mode 400 high-speed mode (write operation), c b ? 100 pf maximum 3.4 mhz high-speed mode (read operation), c b ? 100 pf maximum 3.4 high-speed mode (write operation), c b ? 400 pf maximum 1.7 high-speed mode (read operation), c b ? 400 pf maximum 1.7 t buf bus free time between a stop and start condition standard mode 4.7 s fast mode 1.3 t hd , t sta hold time (repeated) start condition standard mode 4 s fast mode 600 ns high-speed mode 160 9 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated timing requirements (continued) parameter test conditions min max unit t low low period of the scl clock standard mode 4.7 s fast mode 1.3 high-speed mode, c b ? 100 pf maximum 160 ns high-speed mode, c b ? 400 pf maximum 320 t high high period of the scl clock standard mode 4 s fast mode 600 ns high-speed mode, c b ? 100 pf maximum 60 high-speed mode, c b ? 400 pf maximum 120 t su , t sta setup time for a repeated start condition standard mode 4.7 s fast mode 600 ns high-speed mode 160 t su , t dat data setup time standard mode 250 ns fast mode 100 high-speed mode 10 t hd , t dat data hold time standard mode 0 3.45 s fast mode 0 0.9 high-speed mode, c b ? 100 pf maximum 0 70 ns high-speed mode, c b ? 400 pf maximum 0 150 t rcl rise time of scl signal standard mode 20 + 0.1 c b 1000 ns fast mode 20 + 0.1 c b 300 high-speed mode, c b ? 100 pf maximum 10 40 high-speed mode, c b ? 400 pf maximum 20 80 t rcl1 rise time of scl signal after a repeated start condition and after an acknowledge bit standard mode 20 + 0.1 c b 1000 ns fast mode 20 + 0.1 c b 300 high-speed mode, c b ? 100 pf maximum 10 80 high-speed mode, c b ? 400 pf maximum 20 160 t fcl fall time of scl signal standard mode 20 + 0.1 c b 300 ns fast mode 20 + 0.1 c b 300 high-speed mode, c b ? 100 pf maximum 10 40 high-speed mode, c b ? 400 pf maximum 20 80 t rda rise time of sda signal standard mode 20 + 0.1 c b 1000 ns fast mode 20 + 0.1 c b 300 high-speed mode, c b ? 100 pf maximum 10 80 high-speed mode, c b ? 400 pf maximum 20 160 t fda fall time of sda signal standard mode 20 + 0.1 c b 300 ns fast mode 20 + 0.1 c b 300 high-speed mode, c b ? 100 pf maximum 10 80 high-speed mode, c b ? 400 pf maximum 20 160 t su , t sto setup time for stop condition standard mode 4 s fast mode 600 ns high-speed mode 160 c b capacitive load for sda and scl 400 pf 10 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated figure 2. serial interface timing for f/s-mode figure 3. serial interface timing for hs-mode sr p sr t fda t rda t hd;dat t su;sta t hd;sta t su;dat t su;sto t rcl1 t fcl t high t low t low t high t rcl t rcl1 = mcs current source pull-up = r (p) resistor pull-up sdah sclh note a: first rising edge of the sclh signal after sr and after each acknowledge bit. see note a see note a t f t low t r t hd;sta t hd;dat t su;dat t f high t su;sta s sr p s t hd;sta t r t buf t su;sto sda scl 11 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 7.7 typical characteristics table of graphs figure no. led power efficiency vs input voltage figure 4 , figure 5 dc input current vs input voltage figure 6 led current vs led pin headroom voltage figure 7 , figure 8 , figure 9 led current vs led current digital code figure 10 , figure 11 , figure 12 , figure 13 indled current vs led pin headroom voltage figure 14 voltage mode efficiency vs output current figure 15 , figure 16 dc output voltage vs output current figure 17 , figure 18 maximum output current vs input voltage figure 19 dc precharge current vs differential input-output voltage figure 20 , figure 21 valley current limit figure 22 , figure 23 balancing current vs balance pin voltage figure 24 supply current vs input voltage figure 25 standby current vs ambient temperature figure 26 temperature detection threshold figure 27 , figure 28 junction temperature vs port voltage figure 29 figure 4. led power efficiency vs input voltage figure 5. led power efficiency vs input voltage figure 6. dc input current vs input voltage figure 7. led2 current vs led2 pin headroom voltage (hc_sel = 0) 0 100 200 300 400 500 600 700 800 900 400 500 600 700 800 900 1000 1100 1200 1300 1400 led2 pin headroom voltage - mv iled2 = 800 ma iled2 = 700 ma iled2 = 550 ma iled2 = 300 ma iled2 = 450 ma iled2 = 350 ma tps61300 i = 1750 ma, hc_sel = low lim led2 current - ma 0 250 500 750 1000 1250 1500 1750 2000 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 v - input voltage - v i i = 1750 ma, hc_sel = tx-mask = low lim iled1 = 50 ma iled2 = 550 ma iled3 = 2 iled1 = 50 ma iled2 = 600 ma iled3 = 3 iled1 = 50 ma iled2 = 450 ma iled3 = 2 tps61300 iled1 = 50 ma iled2 = 275 ma iled3 = 2 dc input current - ma 0 10 20 30 40 50 60 70 80 90 100 led power efficiency (pled/pin) - % 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 v - input voltage - v i tps61300 iled1 = 50 ma iled2 = 100 ma iled3 = i = 1750 ma, hc_sel = tx-mask = low lim iled1 = 0 ma iled2 = 200 ma iled3 = 10 iled1 = 5 ma iled2 = 150 ma iled3 = 7 iled1 = 50 ma iled2 = 550 ma iled3 = 2 iled1 = 50 ma iled2 = 600 ma iled3 = 3 iled1 = 50 ma iled2 = 450 ma iled3 = 2 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 v - input voltage - v i 0 10 20 30 40 50 60 70 80 90 100 led power efficiency (pled/pin) - % iled2 = 75 ma iled2 = 100 ma iled2 = 150 ma iled2 = 200 ma iled2 = 250 ma tps61300 i = 1750 ma, hc_sel = tx-mask = low led2 channel only lim 12 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated figure 8. led1+led3 current vs led1+led3 pin headroom voltage (hc_sel = 0) figure 9. led2 current vs led2 pin headroom voltage (hc_sel = 1) figure 10. led2 current vs led2 current digital code (hc_sel = 0) figure 11. led1, led3 current vs led1, led3 current digital code (hc_sel = 0) figure 12. led2 current vs led2 current digital code (hc_sel = 0) figure 13. led1, led3 current vs led1, led3 current digital code (hc_sel = 0) 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 led2 pin headroom voltage - mv led2 current - ma tps61305 iled2 = 2050 ma, t = 85c a iled2 = 2050 ma, t = 25c a iled2 = 2050 ma, t = -40c a iled2 = 1775 ma, t = 25c a iled2 = 1775 ma, t = 85c a iled2 = 1775 ma, t = -40c a v = 3.6 v, v = 4.95 v hc_sel = high in out 200 225 250 275 300 325 350 375 400 425 450 200 225 250 275 300 325 350 375 400 425 450 led1, led3 current digital code - ma v = 4.5 v in v = 3.6 v in v = 2.5 v in tps61300 i = 1750 ma, hc_sel = low lim led1, led3 current - ma 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 led2 current digital code - ma v = 4.5 v in v = 3.6 v in tps61300 i = 1750 ma, hc_sel = low lim 200 300 400 500 600 700 800 900 v = 2.5 v in led2 current - ma 25 50 75 100 125 25 50 75 100 125 led1, led3 current digital code - ma v = 4.5 v in v = 3.6 v in v = 2.5 v in led1, led3 current - ma tps61300 i = 1750 ma, hc_sel = low lim 0 25 50 75 100 125 150 175 200 225 250 275 300 0 25 50 75 100 125 150 175 200 225 250 275 300 led2 current digital code - ma v = 2.5 v in v = 4.5 v in v = 3.6 v in led2 current - ma tps61300 i = 1750 ma, hc_sel = low lim 0 100 200 300 400 500 600 700 800 900 400 500 600 700 800 900 1000 1100 1200 1300 1400 led1, led3 pin headroom voltage - mv led1 + led3 current - ma iled1 = iled3 = 400 ma i = 1750 ma, hc_sel = low lim tps61300 iled1 = iled3 = 350 ma iled1 = iled3 = 300 ma iled1 = iled3 = 250 ma 13 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated figure 14. indled current vs indled pin headroom voltage figure 15. efficiency vs output current figure 16. efficiency vs output current figure 17. dc output voltage vs load current figure 18. dc output voltage vs load current figure 19. maximum output current vs input voltage 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 v - input voltage - v i i - output current (max) - ma o v = 4.95 v, i = 1250 ma out lim tps61300 voltage mode regulation v = 5.7 v, i = 1250 ma out lim v = 5.7 v, i = 500 ma out lim v = 4.95 v, i = 250 ma out lim t = 25c a 3.71 3.749 3.787 3.825 3.863 3.902 3.94 3.978 4.016 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 i - output current - ma o v - output voltage (dc) - v o i = 0 ma out i = 100 ma out i = 1000 ma out tps61300 voltage mode regulation v = 3.825 v out i = 1750 ma lim 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 1 10 100 1000 10000 i - output current - ma o v - output voltage (dc) - v o tps61300 voltage mode regulation forced pwm operation pfm/pwm operation v = 3.6 v in v = 2.5 v in v = 4.95 v, i = 1750 ma out lim v = 4.2 v in 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 10000 i - output current - ma o efficiency - % forced pwm operation pfm/pwm operation v = 4.2 v in v = 3.6 v in v = 2.5 v in v = 3 v in tps61300 v = 3.825 v voltage mode regulation out i = 1750 ma lim 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 10000 i - output current - ma o efficiency - % v = 4.2 v in v = 3.6 v in v = 2.5 v in tps61300 v = 4.95 v voltage mode regulation out i = 1750 ma lim v = 3 v in pfm/pwm operation forced pwm operation 0 1 2 3 4 5 6 7 8 9 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 indled pin headroom voltage - v indled current - ma indled = 0011 indled = 0010 indled = 0001 t = 85c a t = 25c a t = -40c a t = 85c a t = 25c a t = -40c a t = 85c a t = 25c a tps61300 v = 3.6 v in t = -40c a 14 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated figure 20. dc precharge current vs differential input ? ? output voltage (hc_sel = 1) figure 21. dc precharge current vs differential input ? ? output voltage (hc_sel = 1) figure 22. valley current limit (hc_sel = 1) figure 23. valley current limit (hc_sel = 1) figure 24. balancing current vs balance pin voltage figure 25. supply current vs input voltage 0 50 100 150 200 250 300 350 400 0 0.6 1.2 1.8 2.4 3 3.6 4.2 differential input - output voltage - v tps61305 v = 3.6 v, t = 25c in a hc_sel = 1 v = 2.5 v, t = 25c in a v = 4.2 v, t = 25c in a dc pre-charge current - ma 0 50 100 150 200 250 300 350 400 0 0.6 1.2 1.8 2.4 3 3.6 4.2 differential input - output voltage - v v = 3.6 v, t = -40c in a v = 3.6 v, t = 25c in a v = 3.6 v, t = 85c in a tps61305 hc_sel = 1 dc pre-charge current - ma -20 -15 -10 -5 0 5 10 15 20 25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 v - balance pin voltage - v bal tps61305 v = 4.95 v, hc_sel = 1 out t = 25c a t = 85c a t = -40c a i - balance pin current - ma bal 1000 500 600 700 800 900 1100 1200 1300 1400 1500 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 v - input voltage - v i i - supply current - a cc m tps61305 v = 5.7 v, t = 25c out a v = 3.825 v, t = 25c out a v = 4.95 v, t = 25c out a v = 4.95 v, t = 85c out a v = 4.95 v, t = -40c out a i = 0 ma enpsm bit = envm bit = 1 out 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 300330 360 390 420 450 480 510 540 570 600 630 660 690 720 750 t = 25c a t = 85c a t = -40c a v = 3.6 v in hc_sel = 1, tx-mask = 1, i bit = 1 lim sample size = 70 i - valley current limit - ma lim sample percentage - % tps61305 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 150165 180 195 210 225 240 255 270 285 300 315 330 345 360 375 i - valley current limit - ma lim sample percentage - % hc_sel = 1, tx-mask = 1, i bit = 0 lim tps61305 t = 25c a t = 85c a t = -40c a v = 3.6 v in sample size = 70 15 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated figure 26. standby current vs ambient temperature (hc_sel = 1) figure 27. temperature detection threshold figure 28. temperature detection threshold figure 29. junction temperature vs port voltage 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 64 65 66 67 68 69 70 71 72 73 74 75 temperature detection (70c threshold) sample percentage - % v = 3.6 v in sample size = 76 tps61305 -50 -25 0 25 50 75 100 125 150 175 200 -0.6 -0.55 -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 port voltage - v t - junction temperature - c j v port port input buffer 100 a m tps61300 i = -100 a port m endcl input tx-mask input envm input 0 2 4 6 8 10 12 14 16 18 20 22 24 26 50 51 52 53 54 55 56 57 58 59 60 temperature detection (55c threshold) sample percentage - % v = 3.6 v in tps61305 sample size = 76 0 0.5 1 1.5 2 2.5 3 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 t - ambient temperature - c a i - standby current - a stby m v = 4.8 v in v = 3.6 v in v = 2.5 v in hc_sel = 1 storage capacitor balanced (i = 0 a) out m tps61305 16 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8 detailed description 8.1 overview the tps6130xx family employs a 2-mhz fixed on-time, pwm current-mode converter to generate the output voltage required to drive up to three high-power leds in parallel. the device integrates a power stage based on an nmos switch and a synchronous pmos rectifier. the device also implements a set of linear low-side current regulators to control the led current when the battery voltage is higher than the diode forward voltage. a special circuit is applied to disconnect the load from the battery during shutdown of the converter. in conventional synchronous rectifier circuits, the back-gate diode of the high-side pmos is forward biased in shutdown and allows current flowing from the battery to the output. this device, however, uses a special circuit which takes the cathode of the back-gate diode of the high-side pmos and disconnects it from the source when the regulator is in shutdown (hc_sel = l). the tps6130xx device cannot only operate as a regulated current source but also as a standard voltage boost regulator featuring power-save mode for improved efficiency at light load. the voltage mode operation can be activated either by a software command or by means of a hardware signal (envm). this additional operating mode can be useful to properly synchronize the converter when supplying other high power consuming devices in the system, such as hands-free audio power amplifiers, or any other component requiring a supply voltage higher than the battery voltage. the tps6130xx device also supports storage capacitor on its output (so called energy storage mode). in this operating mode (hc_sel = h), the inductive power stage is used to charge up the super-capacitor to a user- selectable value. once the charge-up is complete, the leds can be fired up to 1025 ma (led1 and led3) and 2050 ma (led2) without causing a battery overload. in general, a boost converter only regulates output voltages which are higher than the input voltage. this device operates differently. for example, in the voltage mode operation the device is capable of regulating 4.2 v at the output from a battery voltage pulsing as high 5.5 v. to control these applications properly, a down-conversion mode is implemented. if the input voltage reaches or exceeds the output voltage, the converter changes to a down-conversion mode. in this mode, the control circuit changes the behavior of the rectifying pmos. it sets the voltage drop across the pmos as high as needed to regulate the output voltage. this means the power losses in the converter increase. this must be considered for thermal consideration. in direct drive mode (hc_sel = l), the power stage is capable of supplying a maximum total current of roughly 1300 to 1500 ma. the tps61300 provides three constant current inputs, capable of sinking up to 400 ma (led1 and led3) and 800 ma (led2) in flashlight mode. the tps6130xx integrates an i 2 c compatible interface allowing transfers up to 3.4 mbits/s. this communication interface can be used to set the operating mode (shutdown, constant output current mode vs constant output voltage mode), to control the brightness of the external led (dc light and flashlight modes), to adjust the output voltage (between 3.825 v and 5.7 v in 125-mv steps) or to program the safety timer for instance. see register maps . in the tps6130xx device, the dc light and flash can be controlled either by the i 2 c interface or by the means of hardware control signals (endcl and flash_sync). to simplify flashlight synchronization with the camera module, the device offers a flash_sync strobe input pin to turn, with zero latency, the led current from dc light to flashlight. the maximum duration of the flashlight pulse can be limited by means of an internal user programmable safety timer (stim). to avoid the leds to be kept accidentally on in dc light mode by software control, the device implements a 11.2-s watchdog timer. 17 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.2 functional block diagrams figure 30. tps61300 block diagram undervoltage lockout bias supply avin vout sw led2 ref bandgap v ref = 1.238v scl sda i 2 c i/f agnd pgnd flash_sync currentcontrol p p sense fb comparator error amplifier ovp comparator voltage regulation current regulation v ref on /off dac t on control led1 currentcontrol lowside led current regulator p sense fb on / off p led3 vled sense dac sense fb txmask endcl envm indled avin indc [1:0 ] highside led current regulator hot die indicator hc_sel vout bal en hc _sel vout 2 350 k zz r s q q control logic control logic max t on timer slewrate controller oscillator backgate control copyright ? 2016, texas instruments incorporated 18 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated functional block diagrams (continued) figure 31. tps61301 block diagram undervoltage lockout bias supply avin vout sw led2 ref bandgap scl sda i 2 c i/f agnd pgnd flash_sync currentcontrol p p sense fb comparator error amplifier ovp comparator voltage regulation current regulation v ref on/off control logic max t on timer dac t on control backgate control led1 currentcontrol lowside led current regulator p sense fb on/off p led3 vled sense dac sense fb tx mask nreset envm indled avin indc[1:0] highside led current regulator slewrate controller hot die indicator hc_sel vout bal en hc_sel vout 2 zz oscillator r s q q control logic v ref = 1.238v 350 k copyright ? 2016, texas instruments incorporated 19 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated functional block diagrams (continued) figure 32. tps61305, tps61305a block diagrams undervoltage lockout bias supply avin vout sw led2 ref bandgap scl sda i 2 c i/f agnd pgnd flash_sync currentcontrol p p sense fb comparator error amplifier ovp comparator voltage regulation current regulation v ref on/off control logic max t on timer dac t on control backgate control led1 currentcontrol lowside led current regulator p sense fb on/off p led3 vled sense dac sense fb nreset txmask indled avin indc[1:0] highside led current regulator slewrate controller hot die indicator hc_sel vout bal en hc_sel vout 2 zz oscillator r s q q control logic ts avin 23a v ref = 1.05v v ref = 0.345v warning hot v ref = 1.238v 350 k copyright ? 2016, texas instruments incorporated 20 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated functional block diagrams (continued) figure 33. tps61306 block diagram undervoltage lockout bias supply avin vout sw led2 ref bandgap scl sda i 2 c i/f agnd pgnd flash_sync currentcontrol p p sense fb comparator error amplifier ovp comparator voltage regulation current regulation v ref on/off control logic max t on timer dac t on control backgate control led1 currentcontrol lowside led current regulator p sense fb on/off p led3 vled sense dac sense fb endcl txmask indled avin indc[1:0] highside led current regulator slewrate controller hot die indicator hc_sel vout bal en hc_sel vout 2 zz oscillator r s q q control logic ts avin 23a v ref = 1.05v v ref = 0.305v warning hot v ref = 1.238v 350 k copyright ? 2016, texas instruments incorporated 21 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated functional block diagrams (continued) figure 34. timer block diagram block diagram 16-bit prescaler safety timer time-out (to) dimming (dim) timer value (stim) flash_sync t pulse clock edge detect start mode 0 mode 1 current regulator mode C dc light / flash active mode 0 = low mode 1 = high duty-cycle generator (0.8% 8.6%) led1-3 on/off control 0: led1-3 off 1: dc light current level start flash/timer (sft) tx-mask 0: dc light current level 1: flash current level led1-3 current control 350 k w safety timer trigger (stt) 1 01 gpio/pg (gpio bit) port direction (dir) (gpio bit) pwrok port type (pg) dc light safety timer (11.2s) mode 1 mode 0 0: normal operation 1: disable current sink 350 k w copyright ? 2016, texas instruments incorporated 22 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.3 feature description 8.3.1 safety timer accuracy the led strobe timer uses the internal oscillator as reference clock. the timer execution speed (see register3 for more information on stim[2:0]) scales according to the reference clock accuracy. (1) see register3 for more information. (2) see electrical characteristics . table 3. frequency for safety timer oscillator frequency safety timer duration minimum maximum = typical (1 + f acc ) (1) typical typical (2) maximum minimum = typical x (1 ? f acc ) (1) 8.3.2 led failure modes and overvoltage protection if a high-power led fails as a short circuit, the low-side current regulator will limit the maximum output current and the high-power led failure (hplf) flag will be set. if a high-power led fails as an open circuit, the control loop will initially attempt to regulate off of its low-side current regulator feedback signal. this will drive vout higher. because the open-circuited led will never accept its programmed current, v out must be voltage-limited by means of a secondary control loop. the tps6130xx device limits v out according to the overvoltage protection settings (refer to the ovp specification). in this failure mode, v out is either limited to 4.65 v (typical) or 6 v (typical) and the high-power led failure (hplf) flag is set. table 4. overvoltage protection threshold ovp threshold operating conditions 4.65-v typical hc_sel = l and 0000 ov[3:0] 0100 6-v typical hc_sel = h or 0101 ov[3:0] 1111 see led high-current regulators, unused inputs for more information. figure 35. overvoltage protection operation (4.65-v typical) 1.02 v out (nom) 0.98 v out (nom) v out (nom) = 4.2 v ovp threshold dynamic load transient led disconnect 4.65 v 150 mv 23 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.3.3 start-up sequence to avoid high inrush current during start-up, take special care to control the inrush current. when the device enables, the internal start-up cycle starts with the first step, the precharge phase. during precharge, the rectifying switch is turned on until the output capacitor is either charged to a value close to the input voltage or 3.3 v, whichever occurs first. the rectifying switch is current-limited during that phase. the current limit increases with decreasing input to output voltage difference. this circuit also limits the output current under short-circuit conditions at the output. figure 36 shows the typical precharge current vs input minus the output voltage for a specific input voltage. figure 36. typical dc precharge and short-circuit current in direct drive mode (hc_sel = l, tps6130xx), after having precharged the output capacitor, the device starts- up switching and increases its current limit in three steps of typically 250 ma, 500 ma, and full current limit (ilim setting). the current limit transitions from the first to the second step occurs after a milli-second operation. full current limit operation is set once the output voltage has reached its regulation limits. in this mode, the active balancing circuit is disabled. in high-current mode (hc_sel = h), the precharge voltage of the storage capacitor is depending on the input voltage and operating mode (for example, voltage regulation vs current regulation mode). in case the device is set for exclusive current regulation operation (that is, mode_ctrl[1:0] = 01 or 10 and envm = 0), the output capacitor precharge voltage will be close to the input voltage. under all other operating conditions, the precharge voltage will either be close to the input voltage or to approximately 3.3 v, whichever is lower. after having precharged the storage capacitor, the device starts-up switching. during down-mode operation, the inductor valley current is actively limited either to 250 ma or 500 ma (refer to ilim setting). as the device enters boost mode operation, the current limit transitions to its full capability (refer to ilim setting and tx-mask input logic state). as a consequence, the output voltage ramps up linearly and the start-up time needed to reach the programmed output voltage (see register6 (tps61300, tps61301) or register6 (tps61305, tps61305a) for the ov[3:0] bits) will mainly depend on the super-capacitor value and load current. in this mode, the active balancing circuit is enabled. 0 50 100 150 200 250 300 350 400 0 0.6 1.2 1.8 2.4 3 3.6 4.2 differential input - output voltage - v v = 3.6 v, t = 25c in a v = 3.6 v, t = 85c in a v = 3.6 v, t = -40c in a tps61305 hc_sel = 1 dc pre-charge current - ma 24 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.3.4 power good (flash ready) the tps6130xx integrates a power good circuitry that is activated when the device is operating in voltage regulation mode (mode_ctrl[1:0] = 11 or envm = 1). in shutdown mode (mode_ctrl[1:0] = 00, endcl = 0 and envm = 0), the gpio/pg pin state is defined in table 5 . table 5. gpio connection gpiotype gpio/pg shutdown state 0 reset/pulled to ground 1 open-drain depending on the gpio/pg output stage type selection (push-pull or open-drain), the polarity of the power-good output signal (pg) can be inverted or not. the power-good software bit and hardware signal polarity is defined in table 6 . table 6. gpio and pg status gpiotype pg bit gpio/pg output port comments 0: push-pull output 0 0 output is active high signal polarity 1 1 1: open-drain output 0 open-drain output is active low signal polarity 1 low the power good signal is valid when the output voltage is within ? 1.5% and 2.5% of its nominal value. conversely, it is asserted low when the voltage mode operation gets suspended (mode_ctrl[1:0] 11 and envm = 0). figure 37. power good operation (dir = 1, gpiotype = 1) the tps6130xx device uses a control architecture that allows recycling of excessive energy that might be stored in the output capacitor. by reversing the operation of the boost power stage, the converter is capable of transferring energy from its output back into the input source. in this case, the power good signal is deasserted whilst the output voltage is decreasing towards its target value. for example the closest fit voltage the converter can support. see down-mode in voltage regulation mode for additional information. voltage mode request output voltage, v out nom. voltage start-up phase power good bit, (pg) power good output, gpio/pg hi-z hi-z 1.025 v out (nom ) 0.985 v out (nom ) v out (nom ) output voltage down regulation output voltage up regulation forced pwm mode operation forced pwm mode operation (pg) bit 25 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.3.5 led temperature monitoring (tps61305, tps61305a, tps61306) the tps61305, tps61305a, and tps61306 devices monitor the led temperature by measuring the voltage between the ts and agnd pins. an internal current source provides the bias ( 24 a) for a negative- temperature coefficient resistor (ntc), and the ts pin voltage is compared to internal thresholds (1.05 v and 0.345 v) to protect the leds against overheating. the temperature monitoring related blocks are always active in dc light or flashlight modes. in voltage mode operation (mode_ctrl[1:0] = 11), the device only activates the ts input when the ents bit is set to high. in shutdown mode, the led temperature supervision is disabled and the quiescent current of the device is dramatically reduced. the ledwarn and ledhot bits reflect the led temperature. the ledwarn bit is set when the voltage seen at the ts pin is lower than 1.05 v. this threshold corresponds to an led warning temperature value, the device operation is still permitted. while regulating led current (for example, dc light or flashlight modes), the ledhot bit is latched when the voltage seen at the ts pin is lower than 0.345 v. this threshold corresponds to an excessive led temperature value, the device operation is immediately suspended (mode_ctrl[1:0] bits are reset and hotdie[1:0] bits are set). 8.3.6 hot die detector the hot die detector monitors the junction temperature but does not shutdown the device. it provides an early warning to the camera engine to avoid excessive power dissipation thus preventing from thermal shutdown during the next high-power flash strobe. the hot die detector (hotdie[1:0] bits) reflects the instantaneous junction temperature and is always enabled excepted when the device is in shutdown mode (mode_ctrl[1:0] = 00, envm = 0 and endcl = 0). 8.3.7 nreset input: hardware enable and disable some devices out of the tps6130xx family feature a hardware reset pin (nreset). this reset pin allows the device to be disabled by an external controller without requiring an i 2 c write command. under normal operation, the nreset pin must be held high to prevent an unwanted reset. when the nreset is driven low, the i 2 c control interface and all internal control registers are reset to the default states and the part enters shutdown mode. 8.3.8 endcl input: dc light hardware control some devices out of the tps6130xx family feature a dedicated dc light control input (endcl). this logic input can be used to turn on the leds for dc light operation. this hardware control pin can be useful to control the torch light functionality from a separate engine (for example, base-band). in this mode of operation, the dc light safety timer is not activated. the endcl input is only active when the device is programmed into shutdown (mode_ctrl[1:0] = 00) or into voltage regulation mode (mode_ctrl[1:0] = 11 or envm = 1) and the indicator control is turned off (indc[3:0] = 0000). led1 ? 3 inputs are controlled according to enled[3:1] bit settings. 8.3.9 flashlight blanking (tx-mask) in direct drive mode (hc_sel = 0), the tx-mask input signal can be used to disable the flashlight operation, for example, during a rf pa transmission pulse. this blanking function turns the led from flashlight to dc light thereby reducing almost instantaneously the peak current loading from the battery. the tx-mask function has no influence on the safety timer duration. 26 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated figure 38. synchronized flashlight with blanking periods in high-current mode (hc_sel = 1), the tx-mask input pin is also used to dynamically adjusts the device ? s current limit setting which controls the maximum current drawn from the input source. see current limit operation for more information. 8.3.10 undervoltage lockout the undervoltage lockout circuit prevents the device from mis-operation at low input voltages. it prevents the converter from turning on the switch-mosfet, or rectifier-mosfet for battery voltages below 2.3 v. the i 2 c compatible interface is fully functional down to 2.1-v input voltage. 8.3.11 storage capacitor active cell balancing a fully charged super-capacitor will typically have leakage current of under 1 a. the tps6130xx device integrates an active balancing feature to cut the total leakage current from the super-capacitor and balance circuit to less than 1.7 a typically. the device integrates a window comparator monitoring the tap point of the multi-cell super-capacitor. the balancing output (bal) is substantially half the actual output voltage (v out ). if the internal leakage current in one of the capacitors is larger than that in the other, then the voltage at their junction will tend to change in such a way that the voltage on the capacitor with the larger (or largest) leakage current will reduce. when this happens, a current will begin to flow from the bal output in such a direction as to reduce the amount by which the voltage changes. the current that will flow after a long period of steady-state conditions will be approximately equal to the difference between the leakage currents of the pair of capacitors which is being balanced by the circuit. the output resistance of the balancing circuit ( 250 ? ) determines how quickly an imbalance will be corrected. 8.3.12 red light privacy indicator the tps6130xx device provides a high-side linear constant current source to drive low vf leds. the led current is directly regulated off the battery and can be controlled through the indc[3:0] bits. operation is understood best by referring to the figure 39 and figure 40 . flash dc light led current flash_sync tx- mask 27 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated figure 39. red light indicator, configuration 1 figure 40. red light indicator, configuration 2 the device can provide a path to allow for reverse biasing of white leds (see figure 40 ). to do so, the output of the converter (vout) is pulled to ground, thus allowing a reverse current to flow. this mode of operation is only possible when the converter ? s power stage is in shutdown (mode_ctrl[1:0] = 00, envm = 0, endcl = 0 and hc_sel = 0). vbat p p l p p vout d1 d2 backgate control led2 indled avin indc[3:0] high-side led current regulator sw avin p on/off led1 p on/off led3 p hi-z hi- z shutdown actif indc[3:2] = 01 && indc[1:0] 00 v out < tbd v c o c in copyright ? 2016, texas instruments incorporated c in vbat c o p p l p p vout d1 d2 backgate control led2 indled avin indc[3:0] high-side led current regulator sw avin p on/off led1 p on/off led3 p shutdown actif indc [3:2] = 01 && indc[1:0] 00 hi-z hi-z v out < tbd v copyright ? 2016, texas instruments incorporated 28 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.3.13 white led privacy indicator the tps6130xx device features white led drive capability at very low light intensity. to generate a reduced led average current, the device employs a 122-hz fixed frequency pwm modulation scheme. operation is understood best by referring to the timer block diagram. the dc light current is modulated with a duty cycle defined by the indc[3:0] bits. the low light dimming mode can only be activated in the software controlled dc light only mode (mode_ctrl[1:0] = 01, envm = x, endcl = 0) and applies to the leds selected through enled[3:1] bits. in this mode, the dc light safety timeout feature is disabled. figure 41. pwm dimming principle 8.3.14 storage capacitor, precharge voltage calibration high-power leds tend to exhibit a wide forward voltage distribution. the tps6130xx device integrates a self- calibration procedure that can be used to determine the optimum super-capacitor precharge voltage based on the actual worst case led forward voltage and esr of the storage capacitor. this calibration procedure is meant to start-off at a minimum output voltage and can be initiated by setting the selfcal bit (preferably with mode_ctrl[1:0] = 00, envm = 0, endcl = 0). the calibration procedure monitors the sense voltage across the low-side current regulators (according to enled[3:1] bits setting) and registers the worst case led (the led featuring the largest forward voltage). the tps6130xx device automatically sweeps through its output voltage range and performs a short duration flash strobe for each step (see register2 (tps61300, tps61301) or register2 (tps61305, tps61305a, tps61306) for fc13[1:0] and fc2[2:0] bits settings). in direct drive mode (hc_sel = l), the energy is being directly transferred from the battery to the leds. in high- current mode (hc_sel = h), the energy is supplied exclusively by the output reservoir capacitor and the inductive power stage is turned off for the flash strobe period of time. the sequence is stopped as soon as the device detects that each of the low-side current regulators have enough headroom voltage (400-mv typical). the device returns the according output voltage in the register ov[3:0] and sets the selfcal bit. this bit is only being reset at the or restart of a calibration cycle. in other words, when selfcal is asserted the output voltage register (ov[3:0]) returns the result of the last calibration sequence. pwm dimming steps 0.8%, 1.6%, 2.3%, 3.1%, 3.9%, 4.7%, 6.3%, 8.6% i dclight 0 i led (dc ) = i dclight x pwm dimming step t 1 t pwm 29 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated figure 42. led forward voltage self-calibration principle 8.3.15 storage capacitor, adaptive precharge voltage in high-power led camera flash applications, the storage capacitor is supposed to be charged to an optimum voltage level in order to: ? maintain sufficient headroom voltage across the led current regulators for the entire strobe time. ? minimize the power dissipation in the device. high-power leds tend to exhibit large dynamic forward voltage variation relating to own self-heating effects. in addition, the energy storage capacitor (electrochemical double-layer capacitor or super-capacitor) also shows a relatively large effective capacitance and esr spread. the main factors contributing to these variations are: ? flash strobe duration ? temperature ? ageing effects in practice, it normally becomes very challenging to compensate for all these variations and a worst-case design would presumably be too pessimistic. as a consequence, designers would have to give up the benefits that come with the storage capacitor, precharge voltage calibration approach. the tps6130xx device offers the possibility of controlling the storage capacitor precharge voltage in a closed- loop manner. the principle is to dynamically adjust the initial prevoltage to the minimum value, as required for the particular components characteristic and operating conditions. the reference criteria used to evaluate proper operation is the headroom voltage across the led current regulators. in case of a critical headroom voltage (v led1-3 ) at the end of a flash strobe (n cycle), the precharge voltage must be increased before the next capture sequence (n+1 cycle). output voltage, v out power good, pg v bat led flash current, i flash ov[3:0] 0000 0001 0010 0011 0100 0101 ~200 m s feedback sense comparator output v led > 400 mv self-calibration, selfcal bit (write) self-calibration, selfcal bit (read) esr x i led ~200 m s feedback sense comparator information x 30 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated figure 43. storage capacitor, simple adaptive precharge voltage 8.3.16 serial interface description i 2 c is a 2-wire serial interface. the bus consists of a data line (sda) and a clock line (scl) with pullup structures. when the bus is idle , both sda and scl lines are pulled high. all the i 2 c compatible devices connect to the i 2 c bus through open-drain i/o pins, sda and scl. a master device, usually a microcontroller or a digital signal processor, controls the bus. the master is responsible for generating the scl signal and device addresses. the master also generates specific conditions that indicate the start and stop of data transfer. a slave device receives or transmits data on the bus under control of the master device. the tps6130xx device works as a slave and supports the following data transfer modes , as defined in the i 2 c- bus specification: standard mode (100 kbps) and fast mode (400 kbps), and high-speed mode (3.4 mbps). the interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. register contents remain intact as long as supply voltage remains above 2.1 v. the data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as f/s- mode in this document. the protocol for high-speed mode is different from f/s-mode, and it is referred to as hs- mode. the tps6130xx device supports 7-bit addressing; 10-bit addressing and general call address are not supported. the device 7-bit address is defined as 011 0011. 8.4 device functional modes 8.4.1 down-mode in voltage regulation mode in general, a boost converter only regulates output voltages which are higher than the input voltage. the featured devices come with the ability to regulate 4.2 v at the output with an input voltage being has high as 5.5 v. to control these applications properly, a down-conversion mode is implemented. in voltage regulation mode, if the input voltage reaches or exceeds the output voltage, the converter changes to the down-conversion mode. in this mode, the control circuit changes the behavior of the rectifying pmos. it sets the voltage drop across the pmos as high as needed to regulate the output voltage. this means the power losses in the converter increase. this must be considered for thermal consideration. the down-conversion mode is automatically turned off as soon as the input voltage falls about 200 mv below the output voltage. for proper operation in down-conversion mode, the output voltage must not be programmed higher than 5.3 v. take care not to violate the absolute maximum ratings at the sw pins. output voltage, v out power good, pg led flash current, i flash feedback sense comparator output (v led > 400 mv) ledhdr bit esr x i led critical headroom voltage flash_sync 31 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated device functional modes (continued) the tps6130xx device uses a control architecture that allows to recycle excessive energy that might be stored in the output capacitor. by reversing the operation of the boost power stage, the converter is capable of transferring energy from its output back into the input source. in high-current mode (hc_sel = 1), this feature becomes useful to dynamically adjust the output voltage (v out ) depending on the operating conditions. for example, 4.95-v constant output voltage to support audio applications or variable storage capacitor precharge voltage. see storage capacitor, precharge voltage calibration for more information. notice that this reverse operating mode can only perform within an output voltage range higher than the input supply. for example, if the storage capacitor is initially precharged to 4.95 v, the input voltage is around 4.1 v and the target output voltage is set to 3.825 v, the converter will only be able to lower the output node down to the input level. 8.4.2 led high-current regulators, unused inputs the tps6130xx device uses led forward voltage sensing circuitry on led1-3 pins to optimize the power stage boost ratio for maximum efficiency. ti recommends not to leave any of the led1, led2, or led3 pins unused if operations has been selected through enled[3:1] bits, due to the nature of the sensing circuitry. leaving led1- 3 pins unconnected, whilst the respective enledx bits have been set, will force the control loop into high gain and eventually trip the output overvoltage protection. the led1-3 inputs may be connected together to drive one or two leds at higher currents. connecting the current sink inputs in parallel does not affect the internal operation of the tps6130xx. for best operation, ti recommends disabling the led inputs that are not used (see register5 for enled[3:1] bits description). to achieve smooth led current waveforms, the tps61300 device actively controls the led current ramp-up or down sequence. table 7. led current ramp-up or down control vs operating mode direct drive mode (hc_sel = 0) high-current mode (hc_sel = 1) led current ramp-up i step = 25 ma i step = 56.25 ma t rise = 12 s t rise = 0.5 s slew-rate ? 2.08 ma/ s slew-rate ? 112.5 ma/ s led current ramp-down i step = 25 ma i step = 56.25 ma t fall = 0.5 s t fall = 0.5 s slew-rate ? 50 ma/ s slew-rate ? 112.5 ma/ s figure 44. led current slew-rate control in high-current mode (hc_sel = 1), the led current settings are defined as a fixed ratio ( 2.25) versus the direct drive mode values (hc_sel = l). led current time t rise i step t fall 32 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.4.3 power-save mode operation, efficiency the tps6130xx device integrates a power save mode to improve efficiency at light load. in power save mode the converter only operates when the output voltage trips below a set threshold voltage. it ramps up the output voltage with one or several pulses and goes again into power save mode once the output voltage exceeds the set threshold voltage. figure 45. operation in pfm mode and transfer to pwm mode the power save mode can be enabled and disabled through the enpsm bit. in down-conversion mode, power save mode is always active and the device cannot be forced into fixed frequency operation at light loads. the led sense voltage has a direct effect on the converter ? s efficiency. because the voltage across the low-side current regulator does not contribute to the output power (led brightness), the lower the sense voltage the higher the efficiency will be. in direct drive mode (hc_sel = l), the energy is being directly transferred from the battery to the leds. the integrated current control loop automatically selects the minimum boosting ratio to maintain regulation based on the led forward voltage and current requirements. the low-side current regulators will be dropping the voltage difference between the input voltage and the leds forward voltage (v f(led) < v in ). when running in boost mode (v f(led) > v in ), the voltage present at the led1 ? 3 pins of the low-side current regulators will be typically 400 mv leading to high power conversion efficiency. depending on the input voltage and the leds forward voltage characteristic the converter will show efficiency in the range of about 75% to 90%. in high-current mode (hc_sel = h), the device is only supplying a limited amount of energy directly from the battery (dc light, contribution to flash current or voltage regulation mode). during a flash strobe, the bulk of the energy supplied to the leds is provided by the reservoir capacitor. the low-side current regulators will be typically operating with 400-mv headroom voltage. this means the power losses in the device increase and special care must be taken for thermal considerations. 8.4.4 mode of operation: dc light and flashlight operation is understood best by referring to the timer block diagram. depending on the settings of mode_ctrl[1:0] bits the device can enter 4 different operating modes. table 8 details the converter ? s operation for envm = 0. table 8. converter operation for envm = 0 mode_ctrl[1:0] description 00 the device is in shutdown mode. 01 the device is regulating the led current to the dc light current level (dclc bits) regardless of the flash_sync input and start_flash/timer (sft) bit. to avoid device shutdown by dc light safety timeout, mode_ctrl[1:0] needs to be refreshed within less than 11.2 s. 10 the flashlight pulse can be either trigger by a hardware signal (flash_sync) or by a software bit (sft). led strobe pulse follows flash_sync. 11 the device is regulating a constant output voltage according to ov[3:0] bits settings. the low-side led1 ? 3 current sinks are disabled and the leds are disconnected from the output. in this operating mode, the safety timer is disabled. v out nom. pfm mode at light load pwm mode at heavy load pfm ripple about 0.015 x v out 1.013 x v out nom. output voltage 33 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.4.5 flash strobe is level sensitive (stt = 0): led strobe follows flash_sync input flash_sync and (sft) = 0: led operation is set to the dc light current level. to avoid device shutdown by dc light safety timeout, mode_ctrl[1:0] must be refreshed within less than 11.2 s. flash_sync or (sft) = 1: the led is driven at the flashlight current level and the safety timer is running. the maximum duration of the flashlight pulse is defined in the stim[2:0] register. figure 46. dc light operation figure 47. synchronized flashlight strobe figure 48. level sensitive safety timer (timeout) figure 49. level sensitive safety timer (normal operation + timeout) the safety timer is started by: ? a rising edge of flash_sync signal. ? a rising edge of start_flash/timer (sft) bit. the safety timer is stopped by: ? a low level of flash_sync signal or start_flash/timer (sft) bit. ? a timeout signal (to). start-flash/timer (sft) bit is being reset by the timeout (to) signal. 8.4.6 flash strobe is leading edge sensitive (stt = 1): one-shot led strobe when flash_sync and start_flash/timer (sft) are both low the led operation is set to the dc light current level. to avoid device shutdown by dc light safety timeout, mode_ctrl[1:0] needs to be refreshed within less than 11.2 s. the duration of the flashlight pulse is defined in the stim register. the flashlight strobe is started by: ? a rising edge of start_flash/timer (sft) bit. ? a rising edge of flash_sync signal. once running, the timer ignores all kind of triggering signal and only stops after a timeout (to). start- flash/timer (sft) bit is being reset by the timeout (to) signal. flash _sync or (sft ) led control timer stim time-out reset (sf) flash dc light flash_sync or (sft) timer stim led control time-out reset (sf) flash dc light flash flash_sync free free i 2 c bus led current dc/dc turn-on command mode_ctrl [1:0] = 10" dc/dc turn-off command mode_ctrl [1:0] = 00" dc light free free free i 2 c bus led current led turn-on command mode_ctrl [1:0] = 01" led turn-off command mode_ctrl[1:0] = 00" 34 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated figure 50. edge sensitive timer (single trigger event) figure 51. edge sensitive timer (single trigger event) figure 52. edge sensitive timer (multiple trigger events) 8.4.7 current limit operation the current limit circuit employs a valley current sensing scheme. current limit detection occurs during the off time through sensing of the voltage drop across the synchronous rectifier. the detection threshold is user selectable through the ilim bit. the ilim bit can only be set before the device enters operation (that is, initial shutdown state). figure 53 illustrates the inductor and rectifier current waveforms during current limit operation. the output current, i out , is the average of the rectifier ripple current waveform. when the load current is increased such that the lower peak is above the current limit threshold, the off time is lengthened to allow the current to decrease to this threshold before the next on-time begins (so called frequency fold-back mechanism). both the output voltage and the switching frequency are reduced as the power stage of the device operates in a constant current mode. the maximum continuous output current (i out(cl) ), before entering current limit operation, can be defined with equation 1 . (1) the tps6130xx device also provides a negative current limit ( 300 ma) to prevent an excessive reverse inductor current when the power stage sinks current from the output (that is, storage capacitor) in the forced continuous conduction mode. out in in out(cl) valley l l out v v v 1 d i = (1 d) (i + i ) with i = and d 2 l f v - - d d ? flash _sync or (sft ) led control timer stim reset (sft) flash dc light flash_ sync or (sft ) led control timer stim reset (sft) flash dc light flash _sync or (sft ) led control timer stim reset (sft) flash dc light 35 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated figure 53. inductor and rectifier currents in current limit operation to minimize the requirements on the energy storage capacitor present at the output of the driver (hc_sel = 1), the tps6130xx device can contribute to a larger extent in supporting directly the high-current led flash strobe. in fact, the device can dynamically adjust its current limit setting according to the tx-mask input. table 9. inductor current limit operation vs hc_sel and tx-mask inputs current limit setting ilim bit hc_sel input tx-mask input 1250 ma low low low 1750 ma high low low 1250 ma low high low 1750 ma high high low 1250 ma low low high 1750 ma high low high 250 ma low high high 500 ma high high high i in (dc) inductor current rectifier current d i l f d l v i in l = d i l current limit threshold i valley = i lim i in (dc) increased load current i out (cl) d i l f i peak i (= i ) out(dc) led 36 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.4.8 hardware voltage mode selection the tps6130xx device integrates a logic input (envm) or a software control bit (envm bit) that can be used to force the converter to run in voltage mode regulation. pulling the envm pin high forces the device into voltage regulation mode (v out is preset to a fixed value, 4.95 v). this additional operating mode can be useful to supply other high power consuming devices in the system, such as hands-free audio power amplifiers, or any other component requiring a regulated supply voltage higher or lower than the battery voltage. table 10 gives an overview of the different mode of operation. table 10. operating mode description internal register settings mode_ctrl[1:0] envm bit operating modes 00 0 the converter is in shutdown mode and the load is disconnected from the battery. 01 0 leds are turned-on for dc light operation (for example, movie-light). the converter is operating in the current regulation mode (cm). the output voltage is controlled by the forward voltage characteristic of the led. the energy is being directly transferred from the battery to the output. the integrated current control loop automatically selects the minimum boosting ratio to maintain regulation based on the led forward voltage and current requirements. when running in linear mode (v f(led) < v in ), the dc-dc power stage featuring valley-current limit is not active permitting relatively large currents to circulate from the input to the output of the device. 10 0 the converter is operating in the current regulation mode (cm). the output voltage is controlled by the forward voltage characteristic of the led. leds are ready for flashlight operation and dc light operation is supported directly from the battery. the integrated current control loop automatically selects the minimum boosting ratio to maintain regulation based on the led forward voltage and current requirements. when running in linear mode (v f(led) < v in ), the dc-dc power stage featuring valley-current limit is not active permitting relatively large currents to circulate from the input to the output of the device. in high-current mode (hc_sel = h), the energy is supplied by the output reservoir capacitor and the inductive power stage is turned-off for the flash strobe period of time. 11 0 leds are turned-off and the converter is operating in the voltage regulation mode (vm). the output voltage is set through the register ov[3:0]. 00 1 leds are turned-off and the converter is operating in the voltage regulation mode (vm). the output voltage is set through the register ov[3:0]. 01 1 the converter is operating in the voltage regulation mode (vm) and it ? s output voltage is set through the register ov[3:0]. the leds are turned-on for dc light operation and the energy is being directly transferred from the battery to the output. the led currents are regulated by the means of the low-side current sinks. 10 1 the converter is operating in the voltage regulation mode (vm) and it ? s output voltage is set through the register ov[3:0]. the led currents are regulated by the means of the low-side current sinks. the leds are ready for flashlight operation. in direct drive mode (hc_sel = l), the energy is being directly transferred from the battery to the output. in high-current mode (hc_sel = h), the energy is largely supplied by the output reservoir capacitor. the inductive power stage is turned-on to support dc light operation and to contribute the flash strobe itself. 11 1 leds are turned-off and the converter is operating in the voltage regulation mode (vm). the output voltage is set through the register ov[3:0]. 8.4.9 shutdown mode_ctrl[1:0] bits low force the device into shutdown. the shutdown state can only be entered when the voltage regulation and dc light modes are both turned-off (envm = 0 and endcl = 0). in direct drive mode (hc_sel = l), the regulator stops switching, the high-side pmos disconnects the load from the input and the ledx pins are high impedance thus eliminating any dc conduction path. the tps6130xx device actively discharges the output capacitor when it turns off. 37 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated the integrated discharge resistor has a typical resistance of 2 k ? equally split-off between vout to bal and bal to gnd outputs. the required time to discharge the output capacitor at v out depends on load current and the effective output capacitance. the active balancing circuit is disabled and the device consumes only a shutdown current of 1 a (typical). in high-current mode (hc_sel = h), the device maintains its output biased at the input voltage level. in this mode, the synchronous rectifier is current-limited, allowing external load, such as audio amplifiers, to be powered with a restricted supply. the active balancing circuit is enabled and the device consumes only a standby current of 5 a (typical). 8.4.10 thermal shutdown as soon as the junction temperature, t j , exceeds 160 c typical, the device goes into thermal shutdown. in this mode, the power stage and the low-side current regulators are turned off, the hotdie[1:0] bits are set and can only be reset by a readout. in the voltage mode operation (mode_ctrl[1:0] = 11 or envm = 1), the device continues its operation when the junction temperature falls below 140 c (typical) again. in the current regulation mode (that is, dc light or flashlight modes) the device operation is suspended. 8.4.11 f/s-mode protocol the master initiates data transfer by generating a start condition. the start condition is when a high-to-low transition occurs on the sda line while scl is high, as shown in figure 54 . all i 2 c-compatible devices will recognize a start condition. figure 54. start and stop conditions the master then generates the scl pulses, and transmits the 7-bit address and the read/write direction bit r/w on the sda line. during all transmissions, the master ensures that data is valid. a valid data condition requires the sda line to be stable during the entire high period of the clock pulse (see figure 55 ). all devices recognize the address sent by the master and compare it to their internal fixed addresses. only the slave device with a matching address generates an acknowledge (see figure 56 ) by pulling the sda line low during the entire high period of the ninth scl cycle. upon detecting this acknowledge, the master knows that communication link with a slave has been established. figure 55. bit transfer on the serial interface the master generates further scl cycles to either transmit data to the slave (r/w bit 1) or receive data from the slave (r/w bit 0). in either case, the receiver needs to acknowledge the data sent by the transmitter. so an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. data line stable; data valid data clk change of data allowed start condition data clk stop condition s p 38 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated to signal the end of the data transfer, the master generates a stop condition by pulling the sda line from low to high while the scl line is high (see figure 54 ). this releases the bus and stops the communication link with the addressed slave. all i 2 c compatible devices must recognize the stop condition. upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. attempting to read data from register addresses not listed in this section will result in 00h being read out. figure 56. acknowledge on the i 2 c bus figure 57. bus protocol 8.4.12 hs-mode protocol the master generates a start condition followed by a valid serial byte containing hs master code 00001xxx. this transmission is made in f/s-mode at no more than 400 kbps. no device is allowed to acknowledge the hs master code, but all devices must recognize it and switch their internal setting to support 3.4-mbps operation. the master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). after this repeated start condition, the protocol is the same as f/s-mode, except that transmission speeds up to 3.4 mbps are allowed. a stop condition ends the hs-mode and switches all the internal settings of the slave devices to support the f/s-mode. instead of using a stop condition, repeated start conditions must be used to secure the bus in hs-mode. attempting to read data from register addresses not listed in this section will result in 00h being read out. 39 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.4.13 tps6130xx i 2 c update sequence the tps6130xx requires a start condition, a valid i 2 c address, a register address byte, and a data byte for a single update. after the receipt of each byte, tps6130xx device acknowledges by pulling the sda line low during the high period of a single clock pulse. a valid i 2 c address selects the tps6130xx. tps6130xx performs an update on the falling edge of the acknowledge signal that follows the lsb byte. figure 58. write data transfer format in f/s-mode figure 59. read data transfer format in f/s-mode figure 60. data transfer format in hs-mode 8.5 register maps 8.5.1 slave address byte figure 61. slave address byte description msb lsb x x x x x x a1 a0 the slave address byte is the first byte received following the start condition from the master device. 8.5.2 register address byte figure 62. register address byte description msb lsb 0 0 0 0 00 d2 d1 d0 slave address r/w a register address a p sr 1 7 1 1 1 1 8 data 8 a/a 1 s hs-master code a 1 1 8 f/s mode hs mode f/s mode data transferred (n x bytes + acknowledge) hs mode continues slave address sr from master to tps6130x from tps6130x to master a = acknowledge a = acknowledge s = start condition sr = repeated start condition p = stop condition slave address r/w a register address a data a p s 1 7 1 1 1 1 1 8 8 0 write sr 1 slave address r/w 7 1 1 read a 1 from master to tps6130x from tps6130x to master a = acknowledge s = start condition sr = repeated start condition p = stop condition slave address r/w a register address a data a p s 1 7 1 1 1 1 1 8 8 0 write from master to tps6130x from tps6130x to master a = acknowledge s = start condition sr = repeated start condition p = stop condition 40 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated following the successful acknowledgement of the slave address, the bus master will send a byte to the tps6130xx, which will contain the address of the register to be accessed. 8.5.3 register1 (tps61300, tps61301) memory location: 0x01 figure 63. register1 fields 7 6 5 4 3 2 1 0 envm mode_ctrl[1:0] dclc13[1:0] dclc2[2:0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-1 legend: r/w = read/write; r = read only; -n = value after reset (1) when dclc2[2:0] and dclc13[1:0] are both reset, the device operates in voltage regulation mode. the output voltage is set according to ov[3:0]. (2) to ensure a proper transition into voltage mode operation, ti recommends disabling the leds (enled[2:0] bits are reset) before clearing dclc2[2:0] and dclc13[1:0] bits. table 11. (for example, control_revision register) field descriptions bit field type reset description 7 envm r/w 0 enable voltage mode bit. 0: normal operation. 1: forces the device into a constant voltage source. in read mode, the envm bit is automatically updated to reflect the logic state of the envm input pin. 6 ? 5 mode_ctrl[1:0] r/w 00 mode control bits. 00: device in shutdown mode. 01: device operates in dc light mode. 10: device operates in dc light and flash mode. 11: device operates as constant voltage source. to avoid device shutdown by dc light safety timeout, mode_ctrl[1:0] bits need to be refreshed within less than 11.2 s. writing to register1[6:5] automatically updates register2[6:5]. 4 ? 3 dclc13[1:0] r/w 01 dc light current control bits (led1/3). 00: 0 ma. leds are off, v out set according to ov[3:0]. (1) (2) 01: 50 ma 10: 75 ma 11: 100 ma 2 ? 0 dclc2[2:0] r/w 001 dc light current control bits (led2). 000: 0 ma. leds are off, v out set according to ov[3:0]. (1) (2) 001: 50 ma 010: 75 ma 011: 100 ma 100: 125 ma 101: 150 ma 110: 200 ma, 350 ma current level can be activated simultaneously with tx-mask = 1. 111: 250 ma, 500 ma current level can be activated simultaneously with tx-mask = 1. 41 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.5.4 register1 (tps61305, tps61305a, tps61306) memory location: 0x01 figure 64. register1 fields 7 6 5 4 3 2 1 0 envm mode_ctrl[1:0] dclc13[1:0] dclc2[2:0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-1 legend: r/w = read/write; r = read only; -n = value after reset (1) when dclc2[2:0] and dclc13[1:0] are both reset, the device operates in voltage regulation mode. the output voltage is set according to ov[3:0]. (2) to ensure a proper transition into voltage mode operation, ti recommends disabling the leds (enled[2:0] bits are reset) before clearing dclc2[2:0] and dclc13[1:0] bits. table 12. (for example, control_revision register) field descriptions bit field type reset description 7 envm r/w 0 enable voltage mode bit. 0: normal operation. 1: forces the device into a constant voltage source. in read mode, the envm bit is automatically updated to reflect the logic state of the envm input pin. 6 ? 5 mode_ctrl[1:0] r/w 00 mode control bits. 00: device in shutdown mode. 01: device operates in dc light mode. 10: device operates in dc light and flash mode. 11: device operates as constant voltage source. to avoid device shutdown by dc light safety timeout, mode_ctrl[1:0] bits need to be refreshed within less than 11.2 s. writing to register1[6:5] automatically updates register2[6:5]. 4 ? 3 dclc13[1:0] r/w 01 dc light current control bits (led1/3). 00: 0 ma. leds are off, v out set according to ov[3:0]. (1) (2) 01: 55 ma 10: 85 ma 11: 110 ma 2 ? 0 dclc2[2:0] r/w 001 dc light current control bits (led2). 000: 0 ma. leds are off, v out set according to ov[3:0]. (1) (2) 001: 55 ma 010: 85 ma 011: 110 ma 100: 140 ma 101: 165 ma 110: 220 ma, 350 ma current level can be activated simultaneously with tx-mask = 1. 111: 275 ma, 500 ma current level can be activated simultaneously with tx-mask = 1. 42 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.5.5 register2 (tps61300, tps61301) memory location: 0x02 figure 65. register2 fields 7 6 5 4 3 2 1 0 envm mode_ctrl[1:0] fc13[1:0] fc2[2:0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 legend: r/w = read/write; r = read only; -n = value after reset table 13. register2 field descriptions bit field type reset description 7 envm r/w 0 enable voltage mode bit. 0: normal operation. 1: forces the device into a constant voltage source. in read mode, the envm bit is automatically updated to reflect the logic state of the envm input pin. 6 ? 5 mode_ctrl[1:0] r/w 00 mode control bits. 00: device in shutdown mode. 01: device operates in dc light mode. 10: device operates in dc light and flash mode. 11: device operates as constant voltage source. to avoid device shutdown by dc light safety timeout, mode_ctrl[1:0] bits need to be refreshed within less than 11.2 s. writing to register2[6:5] automatically updates register1[6:5]. 4 ? 3 fc13[1:0] r/w 00 flash current control bits (led1/3). hc_sel = 0 000: 275 ma 001: 300 ma 010: 350 ma 011: 450 ma 100: 550 ma 101: 600 ma 110: 700 ma 111: 800 ma hc_sel = 1 000: 650 ma 001: 700 ma 010: 825 ma 011: 1050 ma 100: 1300 ma 101: 1400 ma 110: 1600 ma 111: 1850 ma 2 ? 0 fc2[2:0] r/w 011 flash current control bits (led2). hc_sel = 0 00: 250 ma 01: 300 ma 10: 350 ma 11: 400 ma hc_sel = 1 00: 600 ma 01: 700 ma 10: 800 ma 11: 925 ma 43 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.5.6 register2 (tps61305, tps61305a, tps61306) memory location: 0x02 figure 66. register2 fields 7 6 5 4 3 2 1 0 envm mode_ctrl[1:0] fc13[1:0] fc2[2:0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 legend: r/w = read/write; r = read only; -n = value after reset table 14. register2 field descriptions bit field type reset description 7 envm r/w 0 enable voltage mode bit. 0: normal operation. 1: forces the device into a constant voltage source. in read mode, the envm bit is automatically updated to reflect the logic state of the envm input pin. 6 ? 5 mode_ctrl[1:0] r/w 00 mode control bits. 00: device in shutdown mode. 01: device operates in dc light mode. 10: device operates in dc light and flash mode. 11: device operates as constant voltage source. to avoid device shutdown by dc light safety timeout, mode_ctrl[1:0] bits need to be refreshed within less than 11.2 s. writing to register2[6:5] automatically updates register1[6:5]. 4 ? 3 fc13[1:0] r/w 00 flash current control bits (led1/3). hc_sel = 0 00: 275 ma 01: 335 ma 10: 385 ma 11: 445 ma hc_sel = 1 00: 665 ma 01: 775 ma 10: 890 ma 11: 1025 ma 2 ? 0 fc2[2:0] r/w 011 flash current control bits (led2). hc_sel = 0 000: 305 ma 001: 335 ma 010: 385 ma 011: 500 ma 100: 610 ma 101: 665 ma 110: 775 ma 111: 885 ma hc_sel = 1 000: 720 ma 001: 775 ma 010: 915 ma 011: 1165 ma 100: 1450 ma 101: 1550 ma 110: 1775 ma 111: 2050 ma 44 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.5.7 register3 memory location: 0x03 figure 67. register3 fields 7 6 5 4 3 2 1 0 stim[2:0] hplf selstim (w) to (r) stt sft tx-mask r/w-1 r/w-1 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-1 legend: r/w = read/write; r = read only; -n = value after reset table 15. register3 field descriptions bit field type reset description 7 ? 5 stim[2:0] r/w 110 safety timer bits stim[2:0]: range 0, range 1 000: 68.2 ms, 5.3 ms 001: 102.2 ms, 10.7 ms 010: 136.3 ms, 16.0 ms 011: 170.4 ms, 21.3 ms 100: 204.5 ms, 26.6 ms 101: 340.8 ms, 32.0 ms 110: 579.3 ms, 37.3 ms 111: 852 ms, 207.7 ms 4 hpfl r 0 high-power led failure flag. 0: proper led operation. 1: led failed (open or shorted). high-power led failure flag is reset after readout 3 selstim r 0 safety timer selection range (write only). 0: safety timer range 0. 1: safety timer range 1. to w time-out flag (read only). 0: no time-out event occurred. 1: time-out event occurred. time-out flag is reset at re-start of the safety timer. 2 stt r/w 0 safety timer trigger bit. 0: led safety timer is level sensitive. 1: led safety timer is rising edge sensitive. this bit is only valid for mode_ctrl[1:0] = 10. 1 sft r/w 0 start/flash timer bit. in write mode, this bit initiates a flash strobe sequence. 0: no change in the high-power led current. 1: high-power led current ramps to the flash current level. in read mode, this bit indicates the high-power led status. 0: high-power leds are idle. 1: ongoing high-power led flash strobe. 0 tx-mask r/w 1 flash blanking control bit. in write mode, this bit enables and disables the flash blanking and led current reduction function. 0: flash blanking disabled. 1: led current is reduced to dc light level when tx-mask input is high. in read mode, this flag indicates whether or not the flashlight masking input has been activated. tx-mask flag is reset after readout of the flag. 0: no flash blanking event occurred. 1: tx-mask input triggered. 45 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.5.8 register4 memory location: 0x04 figure 68. register4 fields 7 6 5 4 3 2 1 0 pg hotdie[1:0] ilim inc[3:0] r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 legend: r/w = read/write; r = read only; -n = value after reset (1) the ilim bit can only be set before the device enters operation (initial shutdown state). (2) the output node is internally pulled to ground. this mode is only possible for hc_sel = l. (3) this mode of operation can only be activated for mode_ctrl[1:0] = 01 and endcl = 0. table 16. register4 field descriptions bit field type reset description 7 pg r/w 0 power good bit. in write mode, this bit selects the functionality of the gpio/pg output. 0: pg signal is routed to the gpio port. 1: gpio port value bit is routed to the gpio port. in read mode, this bit indicates the output voltage conditions. 0: the converter is not operating within the voltage regulation limits. 1: the output voltage is within its nominal value. 6 ? 5 hotdie[1:0] r 00 instantaneous die temperature bits. 00: t j < 55 c 01:55 c < t j < 70 c 10: t j > 70 c 11: thermal shutdown tripped. indicator flag is reset after readout. 4 ilim r/w 0 inductor valley current limit bit. (1) current limit setting, ilim-bit setting, hc_sel input level, tx-mask input level 1250 ma, low, low, low 1750 ma, high, low, low 1250 ma, low, high, low 1750 ma, high, high, low 1250 ma, low, low, high 1750 ma, high, low, high 250 ma, low, high, high 500 ma, high, high, high 3 ? 0 indc[3:0] r/w 0000 indicator light control bits. indc[3:0]: privacy indicator indled channel 0000: privacy indicator turned-off 0001: indled current = 2.6 ma 0010: indled current = 5.2 ma 0011: indled current = 7.9 ma 0100: privacy indicator turned-off 0101: indled current = 2.6 ma (2) 0110: indled current = 5.2 ma (2) 0111: indled current = 7.9 ma (2) indc[3:0]: privacy indicator led1 ? 3 channels (3) 1000: 0.8% pwm dimming ratio 1001: 1.6% pwm dimming ratio 1010: 2.3% pwm dimming ratio 1011: 3.1% pwm dimming ratio 1100: 3.9% pwm dimming ratio 1101: 4.7% pwm dimming ratio 1110: 6.3% pwm dimming ratio 1111: 8.6% pwm dimming ratio 46 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.5.9 register5 memory location: 0x05 figure 69. register5 fields 7 6 5 4 3 2 1 0 selfcal enpsm stendcl (r) dir (w) gpio gpiotype enled3 enled2 enled1 r/w-0 r/w-1 r/w-1 r/w-0 r/w-1 r/w-0 r/w-1 r/w-0 legend: r/w = read/write; r = read only; -n = value after reset table 17. register5 field descriptions bit field type reset description 7 selfcal r/w 0 high-current led forward voltage self-calibration start bit. in write mode, this bit enables and disables the output voltage vs led forward voltage and current self-calibration procedure. 0: self-calibration disabled. 1: self-calibration enabled. in read mode, this bit returns the status of the self-calibration procedure. 0: self-calibration ongoing 1: self-calibration done notice that this bit is only being reset at the (re-)start of a calibration cycle. 6 enpsm r/w 1 enable and disable power-save mode bit. 0: power-save mode disabled. 1: power-save mode enabled. 5 stendcl r 1 endcl input status bit (read only). this bit indicates the logic state on the endcl state. this bit is only active in tps61300. dir w gpio direction bit. 0: gpio configured as input. 1: gpio configured as output. 4 gpio r/w 0 gpio port value. this bit contains the gpio port value. 3 gpiotype r/w 1 gpio port type. 0: gpio is configured as push-pull output. 1: gpio is configured as open-drain output. 2 enled3 r/w 0 enable and disable high-current led3 bit. 0: led3 input is disabled. 1: led3 input is enabled. 1 enled2 r/w 1 enable and disable high-current led2 bit. 0: led2 input is disabled. 1: led2 input is enabled. 0 enled1 r/w 0 enable and disable high-current led1 bit. 0: led1 input is disabled. 1: led1 input is enabled. 47 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.5.10 register6 (tps61300, tps61301) memory location: 0x06 figure 70. register6 fields 7 6 5 4 3 2 1 0 not used ledhdr ov[3:0] r/w-0 r/w-0 r/w-0 r-0 r/w-1 r/w-0 r/w-0 r/w-1 legend: r/w = read/write; r = read only; -n = value after reset table 18. register6 field descriptions bit field type reset description 4 ledhdr r 0 led high-current regulator headroom voltage monitoring bit. this bit returns the headroom voltage status of the led high-current regulators. this value is being updated at the end of a flash strobe, before the led current ramp-down phase. 0: low headroom voltage. 1: sufficient headroom voltage. 3 ? 0 ov[3:0] r/w 1001 output voltage selection bits. in read mode, these bits return the result of the high-current led forward voltage self-calibration procedure. in write mode, these bits are used to set the target output voltage (see down- mode in voltage regulation mode ). in applications requiring dynamic voltage control, care must be take to set the new target code after voltage mode operation has been enabled (mode_ctrl[1:0] = 11 or envm bit = 1). ov[3:0]: target output voltage 0000: 3.825 v 0001: 3.950 v 0010: 4.075 v 0011: 4.200 v 0100: 4.325 v 0101: 4.450 v 0110: 4.575 v 0111: 4.700 v 1000: 4.825 v 1001: 4.950 v 1010: 5.075 v 1011: 5.200 v 1100: 5.325 v 1101: 5.450 v 1110: 5.575 v 1111: 5.700 v 48 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.5.11 register6 (tps61305, tps61305a) memory location: 0x06 figure 71. register6 fields 7 6 5 4 3 2 1 0 ents ledhot ledwarn ledhdr ov[3:0] r/w-0 r/w-0 r-0 r-0 r/w-1 r/w-0 r/w-0 r/w-1 legend: r/w = read/write; r = read only; -n = value after reset table 19. register6 field descriptions bit field type reset description 7 ents r/w 0 enable and disable led temperature monitoring. 0: led temperature monitoring disabled. 1: led temperature monitoring enabled 6 ledhot r/w 0 led excessive temperature flag. this bit can be reset by writing a logic level zero. 0: ts input voltage > 0.345 v. 1: ts input voltage < 0.345 v. 5 ledwarn r 0 led temperature warning flag (read only). this flag is reset after readout. 0: ts input voltage > 1.05 v. 1: ts input voltage < 1.05 v. 4 ledhdr r 0 led high-current regulator headroom voltage monitoring bit. this bit returns the headroom voltage status of the led high-current regulators. this value is being updated at the end of a flash strobe, before the led current ramp-down phase. 0: low headroom voltage. 1: sufficient headroom voltage. 3 ? 0 ov[3:0] r/w 1001 output voltage selection bits. in read mode, these bits return the result of the high-current led forward voltage self-calibration procedure. in write mode, these bits are used to set the target output voltage (see down- mode in voltage regulation mode ). in applications requiring dynamic voltage control, care must be take to set the new target code after voltage mode operation has been enabled (mode_ctrl[1:0] = 11 or envm bit = 1). ov[3:0]: target output voltage 0000: 3.825 v 0001: 3.950 v 0010: 4.075 v 0011: 4.200 v 0100: 4.325 v 0101: 4.450 v 0110: 4.575 v 0111: 4.700 v 1000: 4.825 v 1001: 4.950 v 1010: 5.075 v 1011: 5.200 v 1100: 5.325 v 1101: 5.450 v 1110: 5.575 v 1111: 5.700 v 49 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 8.5.12 register7 memory location: 0x07 figure 72. register7 fields 7 6 5 4 3 2 1 0 revid[2:0] r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-1 r-0 r-0 legend: r/w = read/write; r = read only; -n = value after reset (1) bit values may differ depending on the product die revision number. table 20. register7 field descriptions bit field type reset description 2 ? 0 revid[2:0] (1) r 100 silicon revision id. 50 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the tps6130xx can drive up to three white leds in parallel (400-ma, 800-ma, and 400-ma maximum flash current). the extended high-current mode (hc_sel) allows up to 1025-ma, 2050-ma, and 1025-ma flash current. the 2-mhz switching frequency allows the use of small and low profile passive components. 9.2 typical applications 9.2.1 4100-ma two white high-power led flashlight featuring storage capacitor figure 73. 4100-ma two white high-power led flashlight featuring storage capacitor 9.2.1.1 design requirements for this design example, use the parameters listed in table 21 as the input parameters. table 21. tps61305 design requirement design parameter example value input voltage range 2.5 v to 5.5 v output voltage 4.95 v operating freqency 2 mhz vout avin sw c i sw led 1 c o 10 m f pgnd pgnd agnd l 2.2 m h sda scl tps61305 led 2 led 3 d1 d2 2.5 v..5.5 v nreset flash_sync ts gpio/pg indled privacyindicator camera engine i 2 c i/f hc_ sel bal flash ready phone power on 1.8 v 220k ntc tx-mask super-cap copyright ? 2016, texas instruments incorporated 51 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 9.2.1.2 detailed design procedure 9.2.1.2.1 inductor selection a boost converter requires two main passive components for storing energy during the conversion. a boost inductor and a storage capacitor at the output are required. the tps6130xx device integrates a current limit protection circuitry. the valley current of the pmos rectifier is sensed to limit the maximum current flowing through the synchronous rectifier and the inductor. the valley peak current limit (250 ma, 500 ma, 1250 ma, or 1750 ma) is user selectable through the i 2 c interface. to optimize solution size, the tps6130xx device has been designed to operate with inductance values between a minimum of 1.3 h and maximum of 2.9 h. ti recommends a 2.2- h inductance in typical high current white led applications. the highest peak current through the inductor and the power switch depends on the output load, the input and output voltages. estimation of the maximum average inductor current and the maximum inductor peak current can be done using equation 2 and equation 3 : (2) where ? f = switching frequency (2 mhz) ? l = inductance value (2.2 h) ? = estimated efficiency (85%) (3) the losses in the inductor caused by magnetic hysteresis losses and copper losses are a major parameter for total circuit efficiency. 9.2.1.2.2 input capacitor ti recommends low esr ceramic capacitors for good input voltage filtering. ti recommends a 10- f input capacitor to improve transient behavior of the regulator and emi behavior of the total power supply circuit. the input capacitor must be placed as close as possible to the input pin of the converter. 9.2.1.2.3 output capacitor the major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of the converter. this ripple is determined by two parameters of the capacitor, the capacitance and the esr. it is possible to calculate the minimum capacitance needed for the defined ripple, supposing that the esr is zero, by using equation 4 : where ? f is the switching frequency and v is the maximum allowed ripple (4) with a chosen ripple voltage of 10 mv, a minimum capacitance of 10 f is needed. the total ripple is larger due to the esr of the output capacitor. this additional component of the ripple can be calculated using equation 5 : v esr = i out r esr (5) the total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the esr of the capacitor. additional ripple is caused by load transients. this means that the output capacitor has to completely supply the load during the charging phase of the inductor. a reasonable value of the output capacitance depends on the speed of the load transients and the load current during the load change. for the standard current white led application (hc_sel = 0, tps6130xx), a minimum of 3- f effective output capacitance is usually required when operating with 2.2- h (typical) inductors. for solution size reasons, this is usually one or more x5r or x7r ceramic capacitors. out out in min out i (v v ) c f v v - ? d out out in in l(peak) out i v v v d i = + with d = 2 f l (1 d) v - - h out l out in v i i v ? 52 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated depending on the material, size and therefore margin to the rated voltage of the used output capacitor, degradation on the effective capacitance can be observed. this loss of capacitance is related to the dc bias voltage applied. ti recommends ensuring the selected capacitors are showing enough effective capacitance under real operating conditions. to support high-current camera flash application (hc_sel = 1), the converter is designed to work with a low voltage super-capacitor on the output to take advantage of the benefits they offer. a low-voltage super-capacitor in the 0.1-f to 1.5-f range, and with esr larger than 40 m ? , is suitable in the tps6130xx application circuit. for this device the output capacitor must be connected between the vout pin and a good ground connection. 9.2.1.2.4 ntc selection (tps61305, tps61305a, tps61306) the tps61305, tps61305a, and tps61306 require a negative thermistor (ntc) for sensing the led temperature. once the temperature monitoring feature is activated, a regulated bias current ( 24 a) will be driven out of the ts port and produce a voltage across the thermistor. if the temperature of the ntc-thermistor rises due to the heat dissipated by the led, the voltage on the ts input pin decreases. when this voltage goes below the warning threshold, the ledwarn bit in register6 is set. this flag is cleared by reading the register. if the voltage on the ts input decreases further and falls below hot threshold , the ledhot bit in register6 is set and the device goes automatically in shutdown mode to avoid damaging the led. this status is latched until the ledhot flag gets cleared by software. the selection of the ntc-thermistor value strongly depends on the power dissipated by the led and all components surrounding the temperature sensor and on the cooling capabilities of each specific application. with a 220-k ? (at 25 c) thermistor, the valid temperature window is set between 60 c to 90 c. the temperature window can be enlarged by adding external resistors to the ts pin application circuit. to ensure proper triggering of the ledwarn and ledhot flags in noisy environments, the ts signal may require additional filtering capacitance. figure 74. temperature monitoring characteristic 53 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 9.2.1.2.5 checking loop stability the first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals: ? switching node, sw ? inductor current, i l ? output ripple voltage, v out(ac) these are the basic signals that need to be measured when evaluating a switching converter. when the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations the regulation loop may be unstable. this is often a result of improper board layout or l-c combination. as a next step in the evaluation of the regulation loop the load transient response needs to be tested. vout can be monitored for settling time, overshoot or ringing that helps judge the converter's stability. without any ringing, the loop has usually more than 45 of phase margin. because the damping factor of the circuitry is directly related to several resistive parameters, such as mosfet r ds(on) , that are temperature dependant, the loop stability analysis has to be done over the input voltage range, output current range, and temperature range. 9.2.1.3 application curves figure 75. storage capacitor precharge (hc_sel = 1) figure 76. storage capacitor charge-up (hc_sel = 1) figure 77. storage capacitor charge-up (hc_sel = 1) figure 78. storage capacitor charge-up (hc_sel = 1) pg (2 v/div) tps61305(nreset = 1) v(1 v/div) out i(200 ma/div) l envm bit = 1 v = 3.6 v, v = 4.95 v, i = 0 ma in out out enpsm bit = 1, ilim bit = 0, tx-mask = 1, hc_sel = 1 t - time = 1 s/div t - time = 1 s/div i(100ma/div) l v(1v/div) out v = 3.6v, in v = 4.95v i = 0ma out out enpsm bit = 1 tps61305 (nreset = 1) pg (2v/div) hc_sel (2v/div) t - time = 2 s/div i(200ma/div) l v(2v/div) out v = 3.6v, in v = 4.95v i = 0ma out out enpsm bit = 1, ilim bit = 0tx-mask = 1 tps61305(nreset = 1) pg (2v/div) hc_sel, envm (2v/div) t - time = 1 s/div i(500ma/div) l v(1v/div) out v = 3.6v, in v = 4.95v i = 0ma out out enpsm bit = 1, ilim bit = 0tx-mask = 0 tps61305(nreset = 1) pg (2v/div) hc_sel, envm (2v/div) 54 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated figure 79. dc light operation (hc_sel = 1) figure 80. flash sequence (hc_sel = 1) figure 81. flash sequence (hc_sel = 1) figure 82. flash sequence (hc_sel = 1) figure 83. flash sequence (hc_sel = 1) figure 84. flash sequence (hc_sel = 1) pg(2 v/div) tps61305(nreset = 1) led v calibrated circuit, ca. 500 mv led pin headroom pin (e/o strobe) f v(200 mv/div - 4.7 v offset) out i + i (1 a/div) led1 led3 tx-mask input = 1tx-mask bit = 0, ilim bit = 1 enpsm bit = 1, i (1 a/div) led2 dclc13 [1:0] = 00 fc13 [1:0] = 11 dclc2 [2:0] = 000 fc2 [2:0] = 111 v = 3.6 v, v = 4.7 v, all led channels active in out t - time = 10 ms/div pg(2 v/div) tps61305(nreset = 1) led v calibrated circuit, ca. 500 mv led pin headroom pin (e/o strobe) f v(500 mv/div - 4.95 v offset) out i + i (1 a/div) led1 led3 tx-mask input = 1enpsm bit = 1, tx-mask bit = 0, ilim bit = 1 i (1 a/div) led2 dclc13 [1:0] = 00 dclc2 [2:0] = 000 fc13 [1:0] = 11 fc2 [2:0] = 111 v = 3.6 v, v = 4.95 v, all led channels active in out t - time = 50 ms/div tps61305(nreset = 1) v(500 mv/div - 4.95 v offset) out enpsm bit = 1,tx-mask bit = 0, ilim bit = 0 i (1 a/div) led2 dclc2 [2:0] = 000 fc2 [2:0] = 111 v = 3.6 v, v = 4.95 v, led2 channel only in out flash sync(2 v/div) i(500 ma/div) l tx-mask input = 1 t - time = 20 ms/div t - time = 100 ms/div v(500mv/div - 4.95v offset) out v = 3.6v, in v = 4.95v, led2 channel only out enpsm bit = 1,ilim bit = 0, tx-mask = 1 tps61305(nreset = 1) i(1a/div) led2 dclc2[2:0] = 000 fc2[2:0] = 111 flash_sync(2v/div) i(200ma/div) l t - time = 500 ms/div i + i (50ma/div) led1 led3 v(1v/div) out v = 3.6v, in v = 4.95v all led channels active out enpsm bit = 1, ilim bit = 0tx-mask = 1 tps61305(nreset = 1) pg (2v/div) i(50ma/div) led2 dc light turn-on command dc light turn-off command dclc13[1:0] = 01dclc2[2:0] = 010 t - time = 50 ms/div v(200mv/div - 4.95v offset) out v = 3.6v, in v = 4.95v, led2 channel only out enpsm bit = 1,ilim bit = 0, tx-mask = 1 tps61305(nreset = 1) pg (2v/div) i(1a/div) led2 dclc2[2:0] = 000 fc2[2:0] = 111 flash_sync(2v/div) 55 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated figure 85. junction temperature monitoring (hc_sel = 1) figure 86. shutdown (hc_sel = 1) 9.2.2 tps61300 typical application figure 87. tps61300 typical application circuit 9.2.2.1 design requirement for this design example, use the parameters listed in table 22 as the input parameters. table 22. tps61300 design requirement design parameter example value input voltage range 2.5 v to 5.5 v output voltage 4.95 v operating freqency 2 mhz t = 55c j tps61305(nreset = 1) led v calibrated circuit, ca. 500 mv led pin headroom pin (e/o strobe) f dc light = 2 s flash strobe = 35 ms i + i (1 a/div) led1 led3 enpsm bit = 1,tx-mask bit = 0, ilim bit = 1 i (1 a/div) led2 dclc2 [2:0] = 011 fc2 [2:0] = 111 v = 3.6 v, v = 4.7 v, all led channels active in out tx-mask(10 mv/div - -0.55 v offset) t = 25c j dclc13 [1:0] = 01 fc13 [1:0] = 11 t - time = 500 ms/div t - time = 100 s/div v(500mv/div) out v = 3.6v, in i = 0ma out tps61305 (nreset = 1) pg (2v/div) hc_sel (2v/div) vout avin sw c i sw led1 c o 10 m f pgnd pgnd agnd l 2.2 m h sda scl i 2 c i/f tps61300 led2 led3 d1 d2 2.5 v..5.5 v endcl flash_sync tx-mask hc_sel gpio/pg envm indled privacy indicator bal copyright ? 2016, texas instruments incorporated 56 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 9.2.2.2 application curves figure 88. flash sequence (hc_sel = 0) figure 89. tx-masking operation (hc_sel = 0) figure 90. tx-masking operation (hc_sel = 0) figure 91. tx-masking operation (hc_sel = 0) figure 92. low-light dimming mode operation figure 93. pwm operation tps61300, hc_sel = 0 v(500 mv/div - 3.6 v offset) out i(20 ma/div) led2 frequency = 121 hzduty cycle = 6.3 % v = 3.6 v, i = 75 ma in dclight2 t - time = 2 ms/div led2 channel only indc[3:0] = 1110 t - time = 125 ns/div sw(2v/div) i(200ma/div) l v(20mv/div - 4.95v offset) out v = 3.6v, in v = 4.95v i = 300ma, i = 1750ma out out lim forced pwm operationenpsm bit = 0 tps61300, hc_sel = 0 t - time = 5 s/div tx-mask(2v/div) i(200ma/div) led2 i(200ma/div) l tps61300, hc_sel = 0 v = 3.6v, v = 4.95v i = 1750ma in out lim led2 channel only dclc2[2:0] = 110 fc2[2:0] = 111 t - time = 100 s/div tx-mask(2v/div) i(200ma/div) led2 i(500ma/div) l tps61300, hc_sel = 0 v = 3.6v, v = 4.95v i = 1750ma in out lim led2 channel onlydclc2[2:0] = 001 fc2[2:0] = 111 t - time = 500 s/div tx-mask(2v/div) i(200ma/div) led2 tps61300, hc_sel = 0 v = 3.6v, v = 4.95v, i = 1750ma in out lim dclc2[2:0] = 000fc2[2:0] = 100 flash_sync(2v/div) i + (200ma/div) led1 i led3 dclc13[1:0] = 00fc13[1:0] = 01 t - time = 1 ms/div i(500ma/div) led2 tps61300, hc_sel = 0 v = 3.6v, v = 4.95v, i = 1750ma in out lim led2 channel onlydclc2[2:0] = 000 fc2[2:0] = 111 flash_sync(2v/div) led2 pin headroom voltage (1v/div) v(1v/div - 3.6v offset) out 57 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated figure 94. pfm operation figure 95. down-mode operation (voltage mode) figure 96. voltage mode load transient response figure 97. start-up into dc light operation figure 98. start-up into voltage mode operation t - time = 200 s/div endcl(2v/div) i(50ma/div) led2 i(200ma/div) l tps61300, hc_sel = 0 v = 3.6v, v = 4.95v i = 1750ma in out lim led2 channel only dclc2[2:0] = 011 v(2v/div) out t - time = 2 s/div m sw(5v/div) i(200ma/div) l v(100mv/div - 4.95v offset) out v = 3.6v, in v = 4.95v i = 50ma, i = 1750ma out out lim pfm/pwm operationenpsm bit = 1 tps61300 hc_sel = 0 t - time = 2 s/div m sw(5v/div) i(200ma/div) l v(100mv/div - 3.825v offset) out v = 4.2v, in v = 3.825v i = 50ma, i = 1750ma out out lim pfm/pwm operationenpsm bit = 1 tps61300, hc_sel = 0 t - time = 100 s/div envm(2v/div) i(200ma/div) l tps61300, hc_sel = 0 v = 3.6v, v = 4.95v i = 1750ma in out lim i = 0ma, out v(2v/div) out t - time = 50 s/div m i(500ma/div) l v(500mv/div - 4.95v offset) out v = 3.6v, in v = 4.95v i = 1750ma out lim pfm/pwm operationenpsm bit = 1 tps61300, hc_sel = 0 i(500ma/div) out 50ma to 500ma load step 58 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 9.3 system examples 9.3.1 2x 600-ma high-power white led solution featuring privacy indicator figure 99. 2 600-ma high-power white led solution featuring privacy indicator 9.3.2 white led flashlight driver and audio amplifier power supply operating simultaneously figure 100. white led flashlight driver and audio amplifier power supply operating simultaneously vout avin sw c i sw led 1 c o 10 m f pgnd pgnd agnd l 2.2 m h sda scl i 2 c i/f tps61300 led 2 led 3 d1 d 2 2.5v..5.5v endcl flash_sync tx-mask gpio/pg envm indled privacyindicator camera engine rf pa tx active enable apa (bb) enable torch(bb) audio input audio input +5.0 v class-d apa en hc_sel bal copyright ? 2016, texas instruments incorporated vout avin sw c i sw led1 c o 10 m f pgnd pgnd agnd l 2.2 m h sda scl tps61300 led2 led3 d1 d2 2.5 v..5.5 v endcl flash_sync tx-mask gpio/pg envm indled privacyindicator camera engine rf pa tx active i 2 c i/f hc_sel bal copyright ? 2016, texas instruments incorporated 59 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated system examples (continued) 9.3.3 white led flashlight driver and audio amplifier power supply operating simultaneously figure 101. white led flashlight driver and audio amplifier power supply operating simultaneously 9.3.4 white led flashlight driver and audio amplifier power supply exclusive operation figure 102. white led flashlight driver and audio amplifier power supply exclusive operation vout avin sw c i sw led 1 c o 10 m f pgnd pgnd agnd l 2.2 m h sda scl i 2 c i/f tps 61300 led 2 led 3 d1 d2 2.5 v..5.5 v endcl flash_sync tx-mask gpio/pg envm indled privacyindicator camera engine rf pa tx active enable torch (bb) +5.0 v audio input audio input en_apa gain _sel 0:nominal gain 1:-6 db gain enable apa (bb) hc_sel bal copyright ? 2016, texas instruments incorporated vout avin sw c i sw led1 c o 10 m f pgnd pgnd agnd l 2.2 m h sda scl high -speed i 2 c i/f tps61300 led2 led3 d1 d 2 2.5 v..5.5 v endcl flash_sync tx-mask gpio/pg envm indled privacyindicator camera engine rf pa tx active enable torch(bb) +4.2 v audio input audio input class-d apa featuring i 2 c control i/f note: reduce audio gain to allow simultaneous operation together this the camera engine. hc_sel bal copyright ? 2016, texas instruments incorporated 60 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated system examples (continued) 9.3.5 white led flashlight driver and auxiliary lighting zone power supply figure 103. white led flashlight driver and auxiliary lighting zone power supply 9.3.6 tps61300, typical application figure 104. tps61300, typical application vout avin sw c i sw led1 c o 10 m f pgnd pgnd agnd l 2.2 m h sda scl tps61300 led2 led3 d1 d2 2. 5 v.. 5 . 5 v endcl flash_sync tx- mask gpio/pg envm indled privacy indicator camera engine i 2 c i/f hc_sel bal phone power on super-cap copyright ? 2016, texas instruments incorporated voltage mode enable base-band engine dx dy dz p0 p1 p2 sda scl en tca6507 gnd vcc +1.8v base-band engine i 2 c i/f vout avin sw c i sw led1 c o 10 m f pgnd pgnd agnd l 2.2 m h sda scl camera engine i 2 c i/f tps 61300 led2 led3 d1 d2 2.5 v..5.5 v endcl flash_sync tx-mask gpio/pg envm indled privacy indicator camera engine rf pa tx active enable torch (bb) hc_sel bal copyright ? 2016, texas instruments incorporated 61 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated system examples (continued) 9.3.7 tps61301, typical application figure 105. tps61301, typical application 9.3.8 tps61305 typical application figure 106. tps61305, typical application vout avin sw c i sw led1 pgnd pgnd agnd l 2.2 m h sda scl high- speed i 2 c i/f tps61301 led2 led3 d1 d2 2.5 v..5.5 v nreset flash_sync tx-mask hc_sel gpio/pg envm indled privacy indicator bal c o 10 m f super-cap copyright ? 2016, texas instruments incorporated vout avin sw c i sw led1 pgnd pgnd agnd l 2.2 m h sda scl high-speed i 2 c i/f tps61305 led2 led3 d1 d2 2.5 v..5.5 v flash_sync ts hc_sel gpio/pg indled privacy indicator bal ntc tx-mask nreset c o 10 m f super-cap copyright ? 2016, texas instruments incorporated 62 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated system examples (continued) 9.3.9 tps61306, typical application figure 107. tps61306, typical application 10 power supply recommendations the tps6130xx is designed to operate from an input voltage supply range from 2.5 v to 5.5 v. this input supply must be well regulated and capable to supply the required input current. if the input supply is located far from the tps6130xx, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. 11 layout 11.1 layout guidelines as for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. if the layout is not carefully done, the regulator could show stability problems as well as emi problems. therefore, use wide and short traces for the main current path and for the power ground tracks. the input capacitor, output capacitor, and the inductor must be placed as close as possible to the ic. use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. connect these ground nodes at any place close to one of the ground pins of the ic. to lay out the control ground, ti recommends using short traces as well, separated from the power ground traces. this avoids ground shift problems, which can occur due to superimposition of power ground current and control ground current. vout avin sw c i sw led1 pgnd pgnd agnd l 2.2 m h sda scl high-speed i 2 c i/f tps61305 led2 led3 d1 d2 2.5 v..5.5 v flash_sync ts hc _sel gpio /pg indled privacy indicator bal ntc tx -mask endcl c o 10 m f super-cap copyright ? 2016, texas instruments incorporated 63 tps61300 , tps61301 tps61305 , tps61305a, tps61306 www.ti.com slvs957e ? june 2009 ? revised april 2016 product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 11.2 layout example figure 108. suggested layout (top) 11.3 thermal considerations implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. many system-dependant issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power- dissipation limits of a given component. three basic approaches for enhancing thermal performance are listed below: ? improving the power dissipation capability of the pcb design ? improving the thermal coupling of the component to the pcb ? introducing airflow in the system junction-to-ambient thermal resistance is highly application and board-layout dependent. in applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. the maximum junction temperature (t j ) of the tps6130xx is 150 c. the maximum power dissipation is especially critical when the device operates in the linear down mode at high led current. for single pulse power thermal analysis (for example, flashlight strobe), the allowable power dissipation for the device is given by figure 109 . these values are derived using the reference design. figure 109. single pulse power capability 0 1 2 3 4 5 6 7 8 9 10 0 20 40 60 80 100 120 140 160 180 200 pulse width - ms p - single pulse constant power dissipation - w dis t = 65c rise j t = 40c rise j no airflow gnd led1 led2 led3 v in gnd l1 c out c in 1 indled sda flash_syncenvm (tps61300/1) ts (tps61305) b2: sclb3: hc_sel c3: tx_mask d3: endcl (tps61300) d4: gpio/pg nreset (tps61301/5) bal copyright ? 2016, texas instruments incorporated 64 tps61300 , tps61301 tps61305 , tps61305a, tps61306 slvs957e ? june 2009 ? revised april 2016 www.ti.com product folder links: tps61300 tps61301 tps61305 submit documentation feedback copyright ? 2009 ? 2016, texas instruments incorporated 12 device and documentation support 12.1 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 23. related links parts product folder sample & buy technical documents tools & software support & community tps61300 click here click here click here click here click here tps61301 click here click here click here click here click here tps61305 click here click here click here click here click here 12.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks nanofree, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. 12.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. package option addendum www.ti.com 20-jan-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tps61300yffr active dsbga yff 20 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 tps61300 tps61300yfft active dsbga yff 20 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 tps61300 TPS61301YFFR active dsbga yff 20 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 tps61301 tps61301yfft active dsbga yff 20 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 tps61301 tps61305yffr active dsbga yff 20 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 tps61305 tps61305yfft active dsbga yff 20 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 tps61305 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. package option addendum www.ti.com 20-jan-2016 addendum-page 2 (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS61301YFFR dsbga yff 20 3000 180.0 8.4 2.13 2.33 0.69 4.0 8.0 q1 tps61301yfft dsbga yff 20 250 180.0 8.4 2.13 2.33 0.69 4.0 8.0 q1 tps61305yfft dsbga yff 20 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 q1 package materials information www.ti.com 17-sep-2016 pack materials-page 1 *all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TPS61301YFFR dsbga yff 20 3000 182.0 182.0 20.0 tps61301yfft dsbga yff 20 250 182.0 182.0 20.0 tps61305yfft dsbga yff 20 250 182.0 182.0 20.0 package materials information www.ti.com 17-sep-2016 pack materials-page 2 important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all semiconductor products (also referred to herein as ? components ? ) are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in ti ? s terms and conditions of sale of semiconductor products. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. ti assumes no liability for applications assistance or the design of buyers ? products. buyers are responsible for their products and applications using ti components. to minimize the risks associated with buyers ? products and applications, buyers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti components or services are used. information published by ti regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of significant portions of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti components or services with statements different from or beyond the parameters stated by ti for that component or service voids all express and any implied warranties for the associated ti component or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of ti components in its applications, notwithstanding any applications-related information or support that may be provided by ti. buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. buyer will fully indemnify ti and its representatives against any damages arising out of the use of any ti components in safety-critical applications. in some cases, ti components may be promoted specifically to facilitate safety-related applications. with such components, ti ? s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. nonetheless, such components are subject to these terms. no ti components are authorized for use in fda class iii (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. only those ti components which ti has specifically designated as military grade or ? enhanced plastic ? are designed and intended for use in military/aerospace applications or environments. buyer acknowledges and agrees that any military or aerospace use of ti components which have not been so designated is solely at the buyer ' s risk, and that buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti has specifically designated certain components as meeting iso/ts16949 requirements, mainly for automotive use. in any case of use of non-designated products, ti will not be responsible for any failure to meet iso/ts16949. products applications audio www.ti.com/audio automotive and transportation www.ti.com/automotive amplifiers amplifier.ti.com communications and telecom www.ti.com/communications data converters dataconverter.ti.com computers and peripherals www.ti.com/computers dlp ? products www.dlp.com consumer electronics www.ti.com/consumer-apps dsp dsp.ti.com energy and lighting www.ti.com/energy clocks and timers www.ti.com/clocks industrial www.ti.com/industrial interface interface.ti.com medical www.ti.com/medical logic logic.ti.com security www.ti.com/security power mgmt power.ti.com space, avionics and defense www.ti.com/space-avionics-defense microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com omap applications processors www.ti.com/omap ti e2e community e2e.ti.com wireless connectivity www.ti.com/wirelessconnectivity mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2016, texas instruments incorporated |
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